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1. 发明授权

EP1387256B1 Program counter adjustment based on the detection of an instruction prefix 有权
公开(公告)号：EP1387256B1
公开(公告)日：2018-11-21
申请号：EP03291920.1
申请日：2003-07-30
申请人： Texas Instruments Incorporated , TEXAS INSTRUMENTS FRANCE
发明人： Chauvel, Gérard , Lassère, Serge , Kuusela, Maija
IPC分类号： G06F9/318 , G06F9/38
CPC分类号： G06F9/30149 , G06F9/30076 , G06F9/30181 , G06F9/30185 , G06F9/382 , G06F9/3879 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502
摘要： A processor (e.g., a co-processor) comprising a decoder coupled to a pre-decoder, in which the decoder decodes a current instruction in parallel with the pre-decoder pre-decoding a subsequent instruction. In particular, the pre-decoder examines at least five Bytecodes in parallel with the decoder decoding a current instruction. The pre-decoder determines if a subsequent instruction contains a prefix. If a prefix is detected in at least one of the five Bytecodes, a program counter skips the prefix and changes the behavior of the decoder during the decoding of the subsequent instruction.

2. 发明授权

EP1387259B1 Inter-processor control 有权
标题翻译：处理器间控制
公开(公告)号：EP1387259B1
公开(公告)日：2017-09-20
申请号：EP03291924.3
申请日：2003-07-30
申请人： Texas Instruments Incorporated , TEXAS INSTRUMENTS FRANCE
发明人： Chauvel, Gérard , Lasserre, Serge
IPC分类号： G06F9/38
CPC分类号： G06F9/30134 , G06F9/30101 , G06F9/3802 , G06F9/3879 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502 , Y02D10/13
摘要： A system includes a first processor coupled to a second processor. The first and second processors are coupled to memory. The first processor fetches and executes supported instructions until an unsupported instruction is detected. The second processor executes the unsupported instruction. If there are less than a threshold number of consecutive supported instructions before the next unsupported instruction, the second processor loads the instructions in the first processor for execution so that the first processor does not fetch the instructions. If there are more than a threshold number of consecutive supported instructions before the next unsupported instruction, the first processor fetches and executes those instructions.
摘要翻译：一种系统包括耦合到第二处理器的第一处理器。第一和第二处理器连接到存储器。第一个处理器读取并执行支持的指令，直到检测到不支持的指令为止。第二个处理器执行不支持的指令。如果在下一个不支持的指令之前，连续支持指令的数量少于阈值数量，则第二处理器将指令加载到第一处理器中以供执行，以使第一处理器不获取指令。如果在下一个不支持的指令之前有超过阈值数量的连续支持指令，则第一个处理器将获取并执行这些指令。

3. 发明授权

EP1387250B8 Processor that accomodates multiple instruction sets and multiple decode modes 有权
标题翻译：处理器与多个指令集和Mehrfachdecodierungsmodi
公开(公告)号：EP1387250B8
公开(公告)日：2012-02-29
申请号：EP03291917.7
申请日：2003-07-30
申请人： TEXAS INSTRUMENTS INC. , TEXAS INSTRUMENTS FRANCE
发明人： Chauvel, Gerard , D'inverno, Dominique , Lasserre, Serge
IPC分类号： G06F9/30
CPC分类号： G06F9/30134 , G06F9/30101 , G06F9/30149 , G06F9/30174 , G06F9/382 , G06F9/3879 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502

4. 发明授权

EP1442374B1 MULTI-CORE MULTI-THREAD PROCESSOR 有权转让
标题翻译：多个核心多线程处理器
公开(公告)号：EP1442374B1
公开(公告)日：2011-07-27
申请号：EP02770646.4
申请日：2002-10-21
申请人： Oracle America, Inc.
发明人： KOHN, Leslie, D. , OLUKOTUN, Kunle, A. , WONG, Michael, K.
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： H04L47/10 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F3/1423 , G06F9/30007 , G06F9/30043 , G06F9/3851 , G06F9/3879 , G06F9/3891 , G06F11/108 , G06F12/0811 , G06F12/0813 , G06F12/084 , G06F13/1689 , G06F21/72 , G09G2352/00 , G09G2360/121 , G09G2370/022 , G09G2370/20 , G11C11/4074 , H04L29/06 , H04L45/745 , H04L47/2441 , H04L49/90 , H04L49/9057 , H04L49/9089 , H04L69/22 , Y02D10/13 , Y02D10/14
摘要： In one embodiment, a method for efficiently classifying packets for a multi-processor/mutli-thread environment is provided. The method initiates with receiving a packet. Then, header information is extracted form the received packet. Next, a first hash value is calculated. Then, a field of interest in a lookup table is determined from the first hash value. Next, a second hash value is calculated. Then, the second hash value is compared to stored hash values in the field of interest of the lookup table to determine a match between the second hash value and one of the values in the field of interest of the lookup table. If there is a match, the received packet is transmitted to a processor corresponding to the one of the values in the row location of the lookup table. A network interface card and a system for efficiently classifying packets in a multicore/multithread environment are also provided.

5. 发明公开

EP2275926A2 Method and apparatus to attain direct communication between accelerator and instruction sequencer 审中-公开
标题翻译：方法和装置来实现的加速和指令序列控制单元之间的直接通信
公开(公告)号：EP2275926A2
公开(公告)日：2011-01-19
申请号：EP10011935.3
申请日：2006-12-15
申请人： Intel Corporation
发明人： Wang, Hong , Shen, John , Jiang, Hong , Hankins, Richard , Hammarlund, Per , Rodgers, Dion , Chinya, Gauthan , Patel, Baiju , Kaushik, Shiv , Bigbee, Bryant , Sheaffer, Gad , Talgam, Yoav , Yosef, Yuval , Held, James P.
IPC分类号： G06F9/38 , G06F9/318
CPC分类号： G06F9/30145 , G06F9/30 , G06F9/30181 , G06F9/3877 , G06F9/3879 , G06T1/20
摘要： The present invention provides a method and an apparatus wherein a request is communicated directly from a user level application to an accelerator through an accelerator interface and the latter is virtualised so that it is visible to both user level applications and to an operating system.
摘要翻译：本发明提供了一种方法和装置，以worin从用户级应用程序直接传达通过于加速器上于加速器接口的请求，而后者是虚拟所以没有它是可见的，以这两个用户级应用程序和操作系统上。

6. 发明公开

EP2266052A2 OFF-LINE TASK LIST ARCHITECTURE 审中-公开
标题翻译：离线任务，LISTENARCHITEKTUR
公开(公告)号：EP2266052A2
公开(公告)日：2010-12-29
申请号：EP09723836.4
申请日：2009-03-07
申请人： QUALCOMM Incorporated
发明人： CHAUDHURI, Arunava , YAO, Iwen , LIN, Jeremy, H. , GURSKI, Remi , YEN, Kevin, W.
IPC分类号： G06F15/78 , H04M1/725 , G06F9/48
CPC分类号： G06F9/3879 , G06F15/7814
摘要： A flexible and reconfϊgurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub- circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub- circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.
摘要翻译：灵活和可重新配置的数字系统（例如，无线调制解调器）包括一组子电路。每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。子电路的任务管理器可以配置和控制子电路的可配置硬件。中央处理器通过在紧耦合存储器中维护一组任务列表来配置和协调子电路的操作。每个任务列表包括相应子电路的任务指令。子电路的任务管理器从其任务列表读取任务指令，并根据指令控制其相关联的硬件电路。时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

7. 发明公开

EP2232363A2 CO-PROCESSOR FOR STREAM DATA PROCESSING 审中-公开
标题翻译：协处理器处理数据流
公开(公告)号：EP2232363A2
公开(公告)日：2010-09-29
申请号：EP09703079.5
申请日：2009-01-15
申请人： Nokia Corporation
发明人： KOLINUMMI, Pasi , VEHVILAINEN, Juhani
IPC分类号： G06F9/38
CPC分类号： G06F9/3879 , G06F9/3012
摘要： An architecture is shown where a conventional direct memory access structure is replaced with a latency tolerant programmable direct memory access engine, or co-processor, that can handle multiple demanding data streaming operations in parallel. The co-processor concept includes a latency tolerant programmable core with any number of tightly coupled auxiliary units. The co-processor operates in parallel with any number of host processors, thereby reducing the host processors' load as the co-processor is configured to autonomously execute assigned tasks.

8. 发明公开

EP2192482A1 Système multiprocessor sur puce 审中-公开
标题翻译：片上多重测量系统
公开(公告)号：EP2192482A1
公开(公告)日：2010-06-02
申请号：EP09176582.6
申请日：2009-11-20
申请人： Thales
发明人： Yehia, Sami
IPC分类号： G06F9/38 , G06F15/78 , G06F15/80
CPC分类号： G06F9/3879 , G06F15/8007
摘要： L'invention concerne un système multiprocesseur sur puce électronique (300) comprenant au moins deux tuiles de calcul, chacune des tuiles de calcul comportant un processeur généraliste, et des moyens d'accès à un réseau de communication (320), lesdites tuiles de calcul étant reliées entre elles par ledit réseau de communication, ledit système multiprocesseur étant caractérisé en ce que :
- un processeur généraliste mettant en oeuvre un jeu d'instructions qui définit l'ensemble des opérations à exécuter par ledit processeur, les processeurs généralistes ont le même jeu d'instructions ;
- au moins une des tuiles de calcul comprend, en outre, un accélérateur couplé au processeur généraliste accélérant des tâches de calcul dudit processeur généraliste.
摘要翻译：该系统具有用于实现一组指令的通用处理器（GPP），其定义要由处理器执行的一组操作。计算瓦片（310-1,310-4,310-6,310-11,310-14）通过由访问单元访问的通信网络（320）连接在它们之间。计算瓦片包括耦合到处理器的加速器，其中加速器加速处理器的计算任务。每个计算瓦片都具有本地存储器。

9. 发明授权

EP1442355B1 DRAM POWER MANAGEMENT 有权
标题翻译：功率控制DRAM
公开(公告)号：EP1442355B1
公开(公告)日：2010-05-05
申请号：EP02780481.4
申请日：2002-10-18
申请人： SUN MICROSYSTEMS, INC.
发明人： KOHN, Leslie, D.
IPC分类号： G06F1/32
CPC分类号： H04L47/10 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F3/1423 , G06F9/30007 , G06F9/30043 , G06F9/3851 , G06F9/3879 , G06F9/3891 , G06F11/108 , G06F12/0811 , G06F12/0813 , G06F12/084 , G06F13/1689 , G06F21/72 , G09G2352/00 , G09G2360/121 , G09G2370/022 , G09G2370/20 , G11C11/4074 , H04L29/06 , H04L45/745 , H04L47/2441 , H04L49/90 , H04L49/9057 , H04L49/9089 , H04L69/22 , Y02D10/13 , Y02D10/14
摘要： In one embodiment, a method for efficiently classifying packets for a multi-processor/mutli-thread environment is provided. The method initiates with receiving a packet. Then, header information is extracted form the received packet. Next, a first hash value is calculated. Then, a field of interest in a lookup table is determined from the first hash value. Next, a second hash value is calculated. Then, the second hash value is compared to stored hash values in the field of interest of the lookup table to determine a match between the second hash value and one of the values in the field of interest of the lookup table. If there is a match, the received packet is transmitted to a processor corresponding to the one of the values in the row location of the lookup table. A network interface card and a system for efficiently classifying packets in a multicore/multithread environment are also provided.

10. 发明公开

EP2144157A2 Information processing unit, and exception processing method for application-specific instruction 审中-公开
标题翻译：数据处理单元和用于错误处理的应用程序专用命令的方法
公开(公告)号：EP2144157A2
公开(公告)日：2010-01-13
申请号：EP09167859.9
申请日：2001-01-24
申请人： FUJITSU LIMITED
发明人： Kimura, Michihide , Suga, Atsuhiro , Miyake, Hideo , Imai, Satoshi , Nakamura, Yasuki
IPC分类号： G06F9/38
CPC分类号： G06F9/3838 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3861 , G06F9/3879
摘要： The control section of an information processing apparatus is set to a mode of execution of an application- specific operation. When an interruption processing program has been started after interrupting the execution of a program, a context is saved, and thereafter it is confirmed whether the operation mode has been set to a state that an operation exception that occurs during the execution of an application- specific operation instruction is detected or not. When an operation exception has been detected, an application- specific operation exception processing is carried out. Then, the context is restored, and the processing returns from the interruption.
摘要翻译：的信息处理装置的控制部分被设置为针对特定应用的操作的执行的一个模式。时中断中断程序的执行后处理程序已经启动，一个上下文被保存，此后确认是否该操作模式已被设定为一个状态做到操作异常做了专用的执行期间发生操作指令被检测到或没有。当在操作异常被检测到，以针对特定应用的操作的异常处理被执行。然后，上下文被恢复，并且处理从中断返回。

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