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1. 发明公开

EP4321993A3 PROGRAMMABLE MATRIX PROCESSING ENGINE 审中-公开
公开(公告)号：EP4321993A3
公开(公告)日：2024-05-22
申请号：EP23219551.1
申请日：2017-12-18
申请人： INTEL Corporation
发明人： WERNER, Tony L. , KALAIAH, Aravind , KORTHIKANTI, Vijay , LAU, Horace
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06N3/063 , G06N3/084 , G06F9/3001
摘要： In one embodiment, an integrated circuit (IC) chip is provided. The IC chip comprises: a plurality of processing units to collectively execute a matrix multiplication operation with matrix data by performing matrix processing at least partially in parallel, each processing unit of the plurality of processing units to process a portion of the matrix data to perform a corresponding partial matrix operation; a plurality of memories, each memory to store the portion of the matrix data to be processed by a corresponding processing unit of the plurality of processing units; a plurality of interconnects to couple the plurality of processing units, a processing unit of the plurality of processing units to send partial matrix data to a neighboring processing unit of the plurality of processing units or to receive partial matrix data from the neighboring processing unit over a corresponding interconnect; a first controller, wherein responsive to the first controller, the plurality of processing units are to collectively execute the matrix multiplication operation in accordance with at least one matrix multiplication command or instruction specifying a first input matrix and a second input matrix, the plurality of processing units to produce an output matrix by multiplying the first input matrix and the second input matrix; and a plurality of second controllers, each second controller associated with a processing unit of the plurality of processing units, the second controller to retrieve the portion of the matrix data to be processed by a corresponding processing unit of the plurality of processing units from a system memory and to store the portion of the matrix data to a corresponding memory of the plurality of memories.

2. 发明授权

EP3575955B1 INDIRECT MEMORY FETCHER 有权
公开(公告)号：EP3575955B1
公开(公告)日：2024-05-01
申请号：EP19170431.1
申请日：2019-04-19
IPC分类号： G06F9/30 , G06F9/35
CPC分类号： G06F9/35 , G06F9/30043 , G06F9/3004

3. 发明公开

EP3396531A1 VARIABLE PRECISION AND MIX TYPE REPRESENTATION OF MULTIPLE LAYERS IN A NETWORK 有权
公开(公告)号：EP3396531A1
公开(公告)日：2018-10-31
申请号：EP18161840.6
申请日：2018-03-14
申请人： INTEL Corporation
发明人： SAREL, Uzi , COHEN, Ehud , SCHWARTZ, Tomer , ARMON, Amitai , SHADMIY, Yahav , BLEIWEISS, Amit , LEIBOVICH, Gal , DREYFUSS, Jeremie , FAIVISHEVSKY, Lev , BAR-ON, Tomer , FAIS, Yaniv , SUBAG, Jacob
IPC分类号： G06F9/30
CPC分类号： G06N3/08 , G06F9/30014 , G06F9/30025 , G06F9/30043 , G06N3/00 , G06N3/04 , G06N3/063
摘要： In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.

4. 发明公开

EP3350691A1 PREFETCHING ASSOCIATED WITH PREDICATED LOAD INSTRUCTIONS 审中-公开
公开(公告)号：EP3350691A1
公开(公告)日：2018-07-25
申请号：EP16778919.7
申请日：2016-09-13
申请人： Microsoft Technology Licensing, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/38 , G06F12/0862 , G06F9/30
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

5. 发明公开

EP3343355A1 DIMENSION SHUFFLING USING MATRIX PROCESSORS 有权
公开(公告)号：EP3343355A1
公开(公告)日：2018-07-04
申请号：EP17208107.7
申请日：2017-12-18
申请人： INTEL Corporation
发明人： KORTHIKANTI, Vijay Anand R. , KALAIAH, Aravind , WERNER, Tony L. , KHOSROWSHAHI, Amir
IPC分类号： G06F9/30
CPC分类号： G06F15/17343 , G06F9/30032 , G06F9/30043 , G06N3/0436 , G11C5/05
摘要： In one embodiment, a matrix operation may be performed to reorder a plurality of dimensions of an input matrix stored in two-dimensional memory. Data associated with the input matrix may be accessed using one or more strided memory operations, wherein the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of locations that are separated by a particular interval. The data accessed using the one or more strided memory operations may be stored in a result matrix, wherein the data accessed using each strided memory operation is stored in the result matrix in non-transpose form or transpose form.

6. 发明公开

EP3343353A1 PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO CHECK AND STORE INDICATIONS OF WHETHER MEMORY ADDRESSES ARE IN PERSISTENT MEMORY 审中-公开
公开(公告)号：EP3343353A1
公开(公告)日：2018-07-04
申请号：EP17202935.7
申请日：2017-11-21
申请人： INTEL Corporation
发明人： BAGHSORKHI, Sara S. , MARGIOLAS, Christos
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/3004 , G06F9/30043 , G06F9/30058 , G06F9/30101 , G06F12/1009 , G06F12/1027 , G06F15/76 , G06F2212/68
摘要： A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate a source memory address information, and is to indicate a destination architecturally-visible storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result in the destination architecturally-visible storage location. The result to indicate whether a logical memory address corresponding to the source memory address information is in a persistent memory. Other processors, methods, systems, and instructions are disclosed.

7. 发明公开

EP3341834A1 EXCEPTION HANDLING 有权
公开(公告)号：EP3341834A1
公开(公告)日：2018-07-04
申请号：EP16766055.4
申请日：2016-09-09
申请人： ARM Limited
发明人： PARKER, Jason , GRISENTHWAITE, Richard Roy
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3865 , G06F9/30043 , G06F9/30098 , G06F9/3861 , G06F9/45533
摘要： A data processing system (2) includes exception handling circuitry (26) to detect attempted execution of an exception-triggering processing operation which includes transfer of a data value with a given register of a register bank (20). Upon detection of such an exception-triggering processing operation, syndrome data is stored within a syndrome register (32) characterising the exception-triggering processing operation with that syndrome data including the data value. The value may be stored into the syndrome register upon occurrence of the exception in the case of an aborting write instruction. The data value may be stored into the syndrome register by emulating code triggered by exception in the case of an aborting read instruction.

8. 发明授权

EP2695077B1 CONDITIONAL STORE INSTRUCTIONS IN AN OUT-OF-ORDER EXECUTION MICROPROCESSOR 有权转让
公开(公告)号：EP2695077B1
公开(公告)日：2018-06-06
申请号：EP12767932.2
申请日：2012-04-06
申请人： VIA Technologies, Inc.
发明人： HENRY, G. Glenn , COL, Gerard M. , EDDY, Colin , HOOKER, Rodney E. , PARKS, Terry
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/30072 , G06F9/30076 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/3859
摘要： An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction. An out-of-order execution pipeline executes the microinstructions to generate results specified by the instruction.

9. 发明授权

EP2695055B1 CONDITIONAL LOAD INSTRUCTIONS IN AN OUT-OF-ORDER EXECUTION MICROPROCESSOR 有权转让
公开(公告)号：EP2695055B1
公开(公告)日：2018-06-06
申请号：EP12767385.3
申请日：2012-04-06
申请人： VIA Technologies, Inc.
发明人： HENRY, G., Glenn , COL, Gerard, M. , EDDY, Colin , HOOKER, Rodney, E. , PARKS, Terry
IPC分类号： G06F15/00 , G06F9/30
CPC分类号： G06F9/30043 , G06F9/30072 , G06F9/30076 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/3859
摘要： An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction. An out-of-order execution pipeline executes the microinstructions to generate results specified by the instruction.

10. 发明公开

EP3308260A1 MULTIPLE CORE PROCESSOR DEVICE WITH MULTITHREADING 审中-公开
标题翻译：具有多线程的多核心处理器设备
公开(公告)号：EP3308260A1
公开(公告)日：2018-04-18
申请号：EP16734467.0
申请日：2016-06-10
申请人： Mobileye Vision Technologies Ltd.
发明人： KREININ, Yosef , ARBELI, Yosi , DOGON, Gil Israel
IPC分类号： G06F9/30 , G06F9/38 , G06F9/52 , G06F12/0806 , G06F12/08 , G06F9/345 , G06F11/10 , G06F7/00
CPC分类号： G06F12/0875 , G06F7/00 , G06F9/3001 , G06F9/30036 , G06F9/30043 , G06F9/3012 , G06F9/30123 , G06F9/3017 , G06F9/30181 , G06F9/345 , G06F9/3824 , G06F9/3826 , G06F9/3851 , G06F9/3865 , G06F9/3891 , G06F9/526 , G06F11/1008 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F2212/452 , G06F2212/62 , G06T1/0007 , G06T1/20 , G06T3/0093
摘要： A method of calculating warp results, the method may include executing, for each target pixel out of a group of target pixels, a warp calculation process that comprises: receiving, by a first group of processing units of an array of processing units, a first weight and a second weight associated with the target pixel; receiving, by a second group of processing units of the array, values of neighboring source pixels associated with the target pixel; calculating, by the second group, a warp result based on in response to values of the neighboring source pixels and the pair of weights; and providing the warp result to a memory module.

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