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1. 发明公开

EP3339871A1 INLINE WAVE MAJORITY GATE DEVICE 有权转让
公开(公告)号：EP3339871A1
公开(公告)日：2018-06-27
申请号：EP17205462.9
申请日：2017-12-05
申请人： IMEC vzw , Katholieke Universiteit Leuven
发明人： ZOGRAFOS, Odysseas , SOREE, Bart , CIUBOTARU, Florin , ADELMANN, Hanns Christoph
IPC分类号： G01R33/12 , G01R33/18
CPC分类号： H03K19/23 , G01R33/1284 , G01R33/18 , G06F1/04 , H03K19/168
摘要： A majority gate device (200) comprising cells (210) configurable as spin wave generators or spin wave detectors such that the majority gate device comprises: an odd number of spin wave generators (212, 214, 216), and at least one spin wave detector (222); the majority gate device moreover comprises a waveguide (230) adapted for guiding spin waves generated by the spin wave generators. The spin wave generators (212, 214, 216) and the at least one spin wave detector (222) are positioned in an inline configuration along the waveguide (230) such that, in operation, interference of the spin waves generated by the spin wave generators (212, 214, 216) can be detected by the at least one spin wave detector (222). Thereby a signal is obtained which corresponds with a majority operation on the generated spin waves.

2. 发明公开

EP3123537A4 MAGNETIC DOMAIN WALL LOGIC DEVICES AND INTERCONNECT 审中-公开
公开(公告)号：EP3123537A4
公开(公告)日：2018-02-14
申请号：EP14887532
申请日：2014-03-25
申请人： INTEL CORP
发明人： NIKONOV DMITRI E , MANIPATRUNI SASIKANTH , YOUNG IAN A
IPC分类号： H01L43/08 , H03K19/18 , H03K19/23
CPC分类号： H01L43/08 , H01L43/10 , H03K19/18 , H03K19/23
摘要： Described is an apparatus which comprises: first, second, and third free magnetic layers; a first metal layer of first material coupled to the first and third free magnetic layers; and a second metal layer of second material different from the first material, the second metal layer coupled to the second and third free magnetic layers. Described is an STT majority gate device which comprises: a free magnetic layer in a ring; and first, second, third, and fourth free magnetic layers coupled to the free magnetic layer.

3. 发明公开

EP2889774A1 Universal error-correction circuit with fault-tolerant nature, and decoder and triple modular redundancy circuit that apply it 有权
标题翻译：与容错性质和解码器和三模冗余电路，用于使用它们的通用误差校正电路
公开(公告)号：EP2889774A1
公开(公告)日：2015-07-01
申请号：EP14198903.8
申请日：2014-12-18
申请人： Huawei Technologies Co., Ltd.
发明人： Tang, Yangyang , Zhang, Chen-xiong
IPC分类号： G06F11/18 , H03K19/23
CPC分类号： H04L49/557 , G06F11/187 , H03K19/23 , H03M13/1105 , H03M13/27 , H03M13/43 , H03M13/6508
摘要： The present invention provides a universal error-correction circuit with fault-tolerant nature, and a decoder and a triple modular redundancy circuit that apply it, where the universal error-correction circuit with fault-tolerant nature includes: an error-correction unit with fault-tolerant nature implemented by a logic gate, where digital input signals of the error-correction unit with fault-tolerant nature are separately I 0 , I 1 ..., I 2 k -1 , and I 2 k , digital output signals of the error-correction unit with fault-tolerant nature are separately O 0 , O 1 ..., O k -2 , and O k -1 , and the digital input signals and the digital output signals belong to a set {0,1}, where k is a positive integer. The error-correction unit with fault-tolerant nature is configured to: when k=1, set O 0 = I 0 if I 0 = I 1 , and O 0 = I 2 otherwise; and when k>1, set O k -1 = I 2 k -1 if O k -2 =I 2 k -1 , and O k- 1 = I 2 k otherwise. Because a logical relationship between input and output is uniquely certain, the error-correction circuit with fault-tolerant nature may be implemented only by a logic gate. There may be a plurality of specific implementation manners, as long as input and output meet the uniquely certain logical relationship of the present invention. Therefore, the error-correction circuit with fault-tolerant nature provided by the present invention is provided with general commonality.
摘要翻译：本发明提供了具有容错性质的通用误差校正电路，和其中具有容错性质通用纠错电路包括一译码器和一个三模冗余电路并应用它，：具有故障纠错单元 -tolerant性质通过的逻辑门，其中具有容错性质纠错单元的数字输入信号是单独I 0实现，I 1，...，I 2 K-1，和I 2 K，数字输出的信号与容错性质纠错单元分别为O 0，O- 1，...，O-ķ-2，和O K -1，和所述数字输入信号与数字输出信号属于一组{0,1 }，其中k是正整数。与容错性质纠错单元被配置为：当k = 1时，设置O 0 = I 0，如果I 0 = I 1和O 0 = I 2否则; 和当k> 1，O-设定K -1 = I 2 K -1如果可ķ-2 = I 2 K -1，和O = I K-1 2 k否则。因为输入和输出之间的逻辑关系是唯一确定的，与容错性质纠错电路可以仅通过一个逻辑门实现。有可能是具体实施方式的复数，只要输入和输出符合本发明的某些独特的逻辑关系。因此，利用由本发明提供容错性质纠错电路被提供有一般的通用性。

4. 发明授权

EP0741354B1 Multi-operand adder using parallel counters 失效
标题翻译：使用多操作数加法器，并行计数器
公开(公告)号：EP0741354B1
公开(公告)日：2004-07-28
申请号：EP96302538.2
申请日：1996-04-11
申请人： CANON KABUSHIKI KAISHA
发明人： Ichikawa, Takeshi, c/o Canon K.K.
IPC分类号： G06F7/60 , G06F7/50 , G06F7/52 , H03K19/23
CPC分类号： G06F7/5318 , G06F7/509 , G06F7/607 , G06F2207/3836 , G06F2207/4816 , G06F2207/4822 , H03K19/23

5. 发明授权

EP0772143B1 Parallel signal processing circuit 失效
标题翻译： Parallele Signalverarbeitungsschaltung
公开(公告)号：EP0772143B1
公开(公告)日：2003-08-27
申请号：EP96117354.9
申请日：1996-10-29
申请人： CANON KABUSHIKI KAISHA
发明人： Kochi, Tetsunobu
IPC分类号： H03K19/23 , G06F7/00 , G06J1/00 , G06F7/02 , G06F17/15 , G06F7/60 , H03M1/42 , H03M1/80 , G06T7/20
CPC分类号： H03M1/42 , G06F7/00 , G06F7/02 , G06F7/607 , G06F17/15 , G06F2207/025 , G06J1/00 , G06T7/223 , G06T2200/28 , G06T2207/10016 , H03K19/23 , H03M1/804

6. 发明公开

EP0709792A3 Semiconductor device, and operating device, signal converter, and signal processing system using the semiconductor device 失效
标题翻译：半导体电路及其在操作电路的应用中，信号转换器和信号处理系统
公开(公告)号：EP0709792A3
公开(公告)日：1997-07-23
申请号：EP95117008.3
申请日：1995-10-27
申请人： CANON KABUSHIKI KAISHA
发明人： Kochi, Tetsunobu, c/o Canon K.K. , Miyawaki, Mamoru, c/o Canon K.K.
IPC分类号： G06J1/00 , H03M1/42 , H03M1/80
CPC分类号： H03M1/42 , G06F7/02 , G06F7/607 , G06F17/15 , G06F2207/025 , G06J1/00 , G06T7/223 , G06T2207/10016 , H03K19/00315 , H03K19/23 , H03M1/804
摘要： There is disclosed a semiconductor device in which capacitor means (2) are connected to multiple input terminals via latch means (12), and the terminals on one side of the capacitor means are commonly connected to the input of a sense amplifier (5), thereby attaining a reduction of the circuit scale, improvement of the operation speed, saving of the consumption power, reduction of the manufacturing cost, and improvement of the manufacturing yield.
摘要翻译：有圆盘游离缺失在哪个电容器装置共同连接到一读出放大器的输入端的半导体装置（2）连接到经由锁存装置的多个输入端（12），并在电容器装置的一侧上的端子（5）从而达到减少电路规模的，改进的操作速度时，功率消耗的节省，降低制造成本，并且制造成品率的改善。

7. 发明公开

EP0146632A4 CIRCUIT MAJORITAIRE. 失效
标题翻译： MAJORITY电路。
公开(公告)号：EP0146632A4
公开(公告)日：1988-11-02
申请号：EP84902078
申请日：1984-06-01
申请人： SONY CORP
发明人： MAEDA SATORU , NOGUCHI YASUSHI
IPC分类号： H04L1/00 , G06F7/00 , G06F7/76 , G06F11/10 , G06F11/18 , H03K19/23 , H03M13/43
CPC分类号： H03M13/43 , H03K19/23

8. 发明公开

EP0069183A1 Procédé et dispositif pour transmettre des signaux logiques entre microplaquettes 失效
标题翻译：微芯片之间传送逻辑信号的方法和装置。
公开(公告)号：EP0069183A1
公开(公告)日：1983-01-12
申请号：EP81430018.2
申请日：1981-06-25
申请人： International Business Machines Corporation , Compagnie IBM FRANCE
发明人： Brunin, Armand , d'Hervilly, Guy
IPC分类号： H03K19/173
CPC分类号： H04L25/0272 , H03K19/00346 , H03K19/01806 , H03K19/212 , H03K19/23 , H04L25/12
摘要： Le dispositif pour la transmission de signaux entre deux microplaquettes (20 et 21), mettant en oeuvre le procédé de la présente invention, comporte des lignes de transmission (28). Les signaux à transmettre sur les bornes (22-1 à 22-N) sont analysés par un circuit (25) qui fournit un signal de commande d'inversion (en 26) si la configuration des signaux sur les bornes contient un nombre de signaux d'un premier niveau (niveau 0) supérieur ou égal au nombre de signaux d'un second niveau (niveau 1). Les circuits d'attaque (24-1 à 24-N) transmettent les signaux de sortie inversés ou inchangés suivant l'état du signal de commande. Les circuits de réception (30-1 à 30-N) reçoivent les signaux inversés ou non et suivant l'état du signal de commande les inversent ou non.

9. 发明公开

EP3343466A1 METHOD AND APPARATUS FOR A BINARY NEURAL NETWORK MAPPING SCHEME UTILIZING A GATE ARRAY ARCHITECTURE 审中-公开
公开(公告)号：EP3343466A1
公开(公告)日：2018-07-04
申请号：EP17204235.0
申请日：2017-11-28
申请人： INTEL Corporation
发明人： MA, Liwei
IPC分类号： G06N3/063 , H03K19/23
CPC分类号： G06N3/0635 , H03K19/23
摘要： In one embodiment, an apparatus comprises a plurality of bitwise multipliers, a bitwise multiplier of the plurality of bitwise multipliers to multiply a binary synapse weight value of a neural network by a binary activation state value of a neuron of the neural network. The apparatus further comprises a plurality of majority voters, a majority voter of the plurality of majority voters to receive outputs of a first group of bitwise multipliers and to generate a majority result to indicate whether a majority of outputs of the first group of bitwise multipliers are set to a first binary value or a second binary value. The apparatus also comprises a first plurality of reconfigurable connections coupled to outputs of the plurality of bitwise multipliers and inputs of the plurality of majority voters.

10. 发明公开

EP1565987A1 SEU HARD MAJORITY VOTER FOR TRIPLE REDUNDANCY 审中-公开
标题翻译：反对FOR三重冗余软错误选民耐
公开(公告)号：EP1565987A1
公开(公告)日：2005-08-24
申请号：EP03797034.0
申请日：2003-11-20
申请人： Honeywell International Inc.
发明人： FULKERSON, David, E.
IPC分类号： H03K19/003 , H03K19/23
CPC分类号： G11C5/005 , H03K19/23
摘要： Majority voting between triple redundant integrated circuits is used in order to provide an SEU hardened output signal. Accordingly, an input signal is processed in a predetermined manner to provide a first signal, the input signal is processed in the same manner to provide a second signal, and the input signal is also processed in the same manner to provide a third signal. A majority vote is taken between the first, second, and third signals by an SEU immune majority voter circuit, and an output signal is provided corresponding to the majority vote.

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