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    • 1. 发明公开
    • Voltage regulator and resonant gate driver thereof
    • Spannungsregler und harmonanter Gattertreiberdafür
    • EP2890009A1
    • 2015-07-01
    • EP14192749.1
    • 2014-11-12
    • Huawei Technologies Co., Ltd.
    • Tang, YangyangZHANG, Chen-xiong
    • H03K17/0412H02M1/088H02M3/158
    • H03K17/04106H02M1/088H02M3/158H02M2001/009H03K17/04123H03K17/12H03K17/6872H03K17/74H03K2217/009Y02B70/1425
    • The present invention relates to a voltage regulator and a resonant gate driver of the voltage regulator, where the resonant gate driver is configured to drive a first power transistor (110) and a second power transistor (120) and includes: a first control gateway (S1, S3, S5), a second control gateway (S2, S4, S6), and an inductor (LR), where: a first end of the first control gateway (S1, S3, S5) is connected to a first end of the second control gateway (S2, S4, S6); a second end of the first control gateway (S1, S3, S5) is connected to a second end of the second control gateway (S2, S4, S6) by using the inductor (LR); and a third end of the first control gateway (S1, S3, S5) is connected to the first power transistor (110), and a third end of the second control gateway (S2, S4, S6) is connected to the second power transistor (120). The resonant gate driver according to an embodiment of the present invention can reduce a driving period and increase a response speed.
    • 本发明涉及电压调节器和谐振栅极驱动器,其中谐振栅极驱动器被配置为驱动第一功率晶体管(110)和第二功率晶体管(120),并且包括:第一控制网关( S1,S3,S5),第二控制网关(S2,S4,S6)和电感器(LR),其中:第一控制网关(S1,S3,S5)的第一端连接到第一控制网关 第二控制网关(S2,S4,S6); 第一控制网关(S1,S3,S5)的第二端通过使用电感器(LR)连接到第二控制网关的第二端(S2,S4,S6); 并且第一控制网关(S1,S3,S5)的第三端连接到第一功率晶体管(110),第二控制网关(S2,S4,S6)的第三端连接到第二功率晶体管 (120)。 根据本发明的实施例的谐振栅极驱动器可以减少驱动周期并增加响应速度。
    • 2. 发明公开
    • Universal error-correction circuit with fault-tolerant nature, and decoder and triple modular redundancy circuit that apply it
    • 与容错性质和解码器和三模冗余电路,用于使用它们的通用误差校正电路
    • EP2889774A1
    • 2015-07-01
    • EP14198903.8
    • 2014-12-18
    • Huawei Technologies Co., Ltd.
    • Tang, YangyangZhang, Chen-xiong
    • G06F11/18H03K19/23
    • H04L49/557G06F11/187H03K19/23H03M13/1105H03M13/27H03M13/43H03M13/6508
    • The present invention provides a universal error-correction circuit with fault-tolerant nature, and a decoder and a triple modular redundancy circuit that apply it, where the universal error-correction circuit with fault-tolerant nature includes: an error-correction unit with fault-tolerant nature implemented by a logic gate, where digital input signals of the error-correction unit with fault-tolerant nature are separately I 0 , I 1 ..., I 2 k -1 , and I 2 k , digital output signals of the error-correction unit with fault-tolerant nature are separately O 0 , O 1 ..., O k -2 , and O k -1 , and the digital input signals and the digital output signals belong to a set {0,1}, where k is a positive integer. The error-correction unit with fault-tolerant nature is configured to: when k=1, set O 0 = I 0 if I 0 = I 1 , and O 0 = I 2 otherwise; and when k>1, set O k -1 = I 2 k -1 if O k -2 =I 2 k -1 , and O k- 1 = I 2 k otherwise. Because a logical relationship between input and output is uniquely certain, the error-correction circuit with fault-tolerant nature may be implemented only by a logic gate. There may be a plurality of specific implementation manners, as long as input and output meet the uniquely certain logical relationship of the present invention. Therefore, the error-correction circuit with fault-tolerant nature provided by the present invention is provided with general commonality.
    • 本发明提供了具有容错性质的通用误差校正电路,和其中具有容错性质通用纠错电路包括一译码器和一个三模冗余电路并应用它,:具有故障纠错单元 -tolerant性质通过的逻辑门,其中具有容错性质纠错单元的数字输入信号是单独I 0实现,I 1,...,I 2 K-1,和I 2 K,数字输出的信号 与容错性质纠错单元分别为O 0,O- 1,...,O-ķ-2,和O K -1,和所述数字输入信号与数字输出信号属于一组{0,1 },其中k是正整数。 与容错性质纠错单元被配置为:当k = 1时,设置O 0 = I 0,如果I 0 = I 1和O 0 = I 2否则; 和当k> 1,O-设定K -1 = I 2 K -1如果可ķ-2 = I 2 K -1,和O = I K-1 2 k否则。 因为输入和输出之间的逻辑关系是唯一确定的,与容错性质纠错电路可以仅通过一个逻辑门实现。 有可能是具体实施方式的复数,只要输入和输出符合本发明的某些独特的逻辑关系。 因此,利用由本发明提供容错性质纠错电路被提供有一般的通用性。