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1. 发明授权

EP2579696B1 CIRCUIT BOARD AND ELECTRONIC DEVICE USING THE SAME 有权
公开(公告)号：EP2579696B1
公开(公告)日：2018-12-05
申请号：EP11786762.2
申请日：2011-05-27
申请人： Kyocera Corporation
发明人： ABE,Yuuichi , NAKAMURA,Kiyotaka , TANIGUCHI,Youhei
IPC分类号： H05K1/09 , H01L23/373 , H05K1/02 , H05K1/03 , H01L23/00 , H01L25/065 , H01L25/07
CPC分类号： H01L23/3735 , H01L24/32 , H01L24/83 , H01L25/0655 , H01L25/072 , H01L2224/32225 , H01L2224/83192 , H01L2224/83447 , H01L2924/01012 , H01L2924/01019 , H01L2924/01322 , H01L2924/1203 , H01L2924/12041 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/3511 , H05K1/0209 , H05K1/0271 , H05K1/0306 , H05K1/09 , H05K2201/0338 , H05K2201/10166 , H01L2924/3512 , H01L2924/00
摘要： Provided are a circuit board and an electronic device using the same, wherein little distortion of a circuit member is caused due to the heat generated by the operation of an electronic component which is mounted on the circuit member and the circuit board has reliability in high heat dissipation performance. A circuit board (10) is configured such that a circuit member (2) which is made primarily of copper is provided on one principal surface of a supporting substrate (1) and the upper surface of the circuit member (2) serves as a mounting surface for electronic components, wherein the circuit member (2) is provided with a first region having a first average grain size and a second region located closer to the mounting surface side than the first region and having a second average grain size smaller than the first grain size.

2. 发明授权

EP2973683B1 PRINTING COMPLEX ELECTRONIC CIRCUITS 有权
公开(公告)号：EP2973683B1
公开(公告)日：2018-10-24
申请号：EP14719954.1
申请日：2014-03-13
申请人： Nthdegree Technologies Worldwide Inc.
发明人： RAY, William Johnstone , BLANCHARD, Richard Austin , LOWENTHAL, Mark David , ORAW, Bradley Steven
IPC分类号： H01L21/98 , H01L25/065 , H01L25/075 , H01L33/20 , H01L21/60 , H05K1/02 , H05K3/12
CPC分类号： H01L24/95 , H01L21/563 , H01L23/3121 , H01L24/06 , H01L24/24 , H01L24/25 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L25/0655 , H01L25/072 , H01L25/0753 , H01L25/18 , H01L25/50 , H01L33/20 , H01L2221/68381 , H01L2224/06181 , H01L2224/24137 , H01L2224/25105 , H01L2224/25174 , H01L2224/32225 , H01L2224/73267 , H01L2224/82101 , H01L2224/82104 , H01L2224/82143 , H01L2224/92244 , H01L2224/95085 , H01L2224/95101 , H01L2224/95102 , H01L2224/95115 , H01L2224/95143 , H01L2224/95146 , H01L2924/10253 , H01L2924/12 , H01L2924/1203 , H01L2924/12041 , H01L2924/13 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H05K1/029 , H05K1/0296 , H05K3/12
摘要： A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

3. 发明公开

EP3389090A1 POWER ELECTRONICS MODULE 无效
公开(公告)号：EP3389090A1
公开(公告)日：2018-10-17
申请号：EP17166088.9
申请日：2017-04-11
申请人： ABB Schweiz AG , Audi AG
发明人： Schuderer, Jürgen , Justin, Villard , Mohn, Fabian , Liu, Chunlei , Apelsmeier, Andreas , Asam, Johann
IPC分类号： H01L23/49 , H01L23/492 , H01L23/34 , H01L25/07 , H01L25/11
CPC分类号： H01L24/48 , H01L23/34 , H01L24/20 , H01L24/37 , H01L24/40 , H01L24/41 , H01L25/071 , H01L25/074 , H01L25/117 , H01L2223/6627 , H01L2224/29339 , H01L2224/32014 , H01L2224/37147 , H01L2224/40095 , H01L2224/41174 , H01L2224/4824 , H01L2224/4826 , H01L2224/48491 , H01L2224/83101 , H01L2224/83447 , H01L2224/83801 , H01L2224/83825 , H01L2224/8384 , H01L2224/84447 , H01L2224/8484 , H01L2924/00014 , H01L2924/09701 , H01L2924/10272 , H01L2924/1203 , H01L2924/13055 , H01L2924/13091 , H01L2924/19104 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A power electronics module (10) comprises a substrate (12) with a substrate metallization layer (14), which is separated into conducting areas (16, 18) for providing conducting paths for the power electronics module (10); a semiconductor switch chip (26) bonded with a first power electrode (28) to a first conducting area (18) of the substrate metallization layer (14); a conductor plate (34, 34') bonded to a second power electrode (30) of the semiconductor switch chip (26) opposite to the first power electrode (28); and a gate conductor (40, 40') bonded to a gate electrode (32) of the semiconductor switch chip (26) besides the second power electrode (30); wherein the conductor plate (34, 34') extends to a second conducting area (16) of the substrate metallization layer (14) and the gate conductor (40, 40') runs through an opening (38) in the conductor plate (34, 34') arranged above the gate electrode (32).

4. 发明授权

EP2884650B1 POWER MODULE COMPRISING TWO ELEMENTS, AND THREE-LEVEL POWER CONVERSION DEVICE USING SAME 有权
公开(公告)号：EP2884650B1
公开(公告)日：2018-09-19
申请号：EP12882834.0
申请日：2012-08-10
申请人： Mitsubishi Electric Corporation
发明人： NAKASHIMA, Yukio
IPC分类号： H02M7/487 , H01L25/11 , H05K7/02 , H05K7/14
CPC分类号： H02M7/537 , H01L25/072 , H01L25/115 , H01L25/117 , H01L2924/10254 , H01L2924/10272 , H01L2924/1033 , H01L2924/1203 , H01L2924/13091 , H02M7/003 , H02M7/487 , H05K7/1432
摘要： A first electrode M1 that is connected to a higher-side potential portion of a first element pair 10, a second electrode M2 that is connected to a connection portion between a lower-side potential portion of the first element pair 10 and a higher-side potential portion of a second element pair 12, and a third electrode M3 that is connected to a lower-side potential portion of the second element pair 12, are provided on one of the main-surface sides of a module casing. The first electrode M1 and the third electrode M3 are arrayed in a direction orthogonal to a longitudinal direction of the module casing on one of the end sides in the longitudinal direction. The second electrode M2 is arranged on the other end side in the longitudinal direction of the module casing. Three dual-element triple-terminal power modules with the same configuration, configured as described above, are used to configure a three-level power converter of one phase.

5. 发明公开

EP3343600A1 HALBLEITERMODUL MIT EINEM ERSTEN UND EINEM ZWEITEN VERBINDUNGSELEMENT ZUM VERBINDEN EINES HALBLEITERCHIPS SOWIE HERSTELLUNGSVERFAHREN 审中-公开
公开(公告)号：EP3343600A1
公开(公告)日：2018-07-04
申请号：EP16207050.2
申请日：2016-12-28
申请人： Siemens Aktiengesellschaft
发明人： Zaiser, Georg
IPC分类号： H01L23/00 , H01L25/07
CPC分类号： H01L24/24 , H01L24/40 , H01L24/48 , H01L24/82 , H01L24/85 , H01L24/92 , H01L25/072 , H01L25/50 , H01L2224/02163 , H01L2224/24011 , H01L2224/2402 , H01L2224/24051 , H01L2224/24137 , H01L2224/245 , H01L2224/40137 , H01L2224/45014 , H01L2224/4846 , H01L2224/48472 , H01L2224/82101 , H01L2224/82106 , H01L2224/92137 , H01L2924/00014 , H01L2924/1203 , H01L2924/1304 , H01L2924/13055 , H01L2924/13091 , H01L2924/15787 , H01L2924/01029 , H01L2924/01013 , H01L2924/01079 , H01L2224/45099
摘要： Die Erfindung betrifft ein Halbleitermodul (1) mit einem Substrat (2), mit einem Halbleiterchip (6), welcher auf dem Substrat (2) angeordnet ist, und mit einem ersten Verbindungselement (12) zum elektrischen Verbinden des Halbleiterchips (6) mit einer Leiterbahn (7) und/oder einem weiteren Bauelement des Halbleitermoduls (1), wobei das erste Verbindungselement (12) zumindest bereichsweise flächig an dem Halbleiterchip (6) und dem Substrat (2) sowie der Leiterbahn (7) und/oder dem weiteren Bauelement anliegt, wobei das Halbleitermodul (1) ein zweites Verbindungselement (13) zum elektrischen Verbinden des Halbleiterchips (6) mit der Leiterbahn (7) und/oder dem weiteren Bauelement aufweist, wobei das zweite Verbindungselement (13) als Draht oder als Band ausgebildet ist.

6. 发明授权

EP3111476B1 VERBESSERTE SCHEIBENZELLE FÜR MEHRERE DRUCKKONTAKTIERTE HALBLEITERBAUELEMENTE 有权转让
标题翻译：用于几种压力接触的半导体元件的改进的光盘单元
公开(公告)号：EP3111476B1
公开(公告)日：2018-04-04
申请号：EP15706201.9
申请日：2015-02-17
申请人： Infineon Technologies Bipolar GmbH & Co. KG , Siemens Aktiengesellschaft
发明人： SCHENK, Mario , PRZYBILLA, Jens , BARTHELMESS, Reiner , DORN, Jörg
IPC分类号： H01L25/07 , H01L23/051 , H01L23/473 , H01L23/48
CPC分类号： H01L25/115 , H01L23/051 , H01L23/32 , H01L23/3675 , H01L23/4006 , H01L23/473 , H01L24/72 , H01L25/072 , H01L2924/1203 , H01L2924/1301 , H01L2924/13055 , H01L2924/00

7. 发明授权

EP3097585B1 POWER SEMICONDUCTOR DEVICE 有权转让
标题翻译：功率半导体器件
公开(公告)号：EP3097585B1
公开(公告)日：2018-02-07
申请号：EP14815341.4
申请日：2014-12-17
申请人： ABB Schweiz AG
发明人： HOMOLA, Jaroslav , DORT, Ladislav , RADVAN, Ladislav
IPC分类号： H01L23/00 , H01L23/62 , H01L23/051
CPC分类号： H01L23/562 , H01L23/051 , H01L23/10 , H01L23/62 , H01L2924/0002 , H01L2924/1203 , H01L2924/1301 , H01L2924/00
摘要： A power semiconductor device is disclosed having a power semiconductor element with an upper and lower side, the upper side being located opposite to the lower side; a first and second electrode, and a housing, wherein the power semiconductor element is arranged between the first and second electrode such, that the upper side comprises a first contact portion being in contact with the first electrode and a first free portion not being in contact with the first electrode, and wherein the lower side at least comprises a second contact portion being in contact with the second electrode, and wherein a channel is provided fluidly connecting at least a part of the first free portion with a predetermined degassing point of the housing for guiding an overpressure, which overpressure results from plasma and/or gas occurring in a failure mode, from the first free portion to the predetermined degassing point.

8. 发明公开

EP2624297A4 POWER SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SAME 有权转让
公开(公告)号：EP2624297A4
公开(公告)日：2018-01-17
申请号：EP11828710
申请日：2011-09-05
申请人： HITACHI AUTOMOTIVE SYSTEMS LTD
发明人： IDE EIICHI , HIRAMITSU SHINJI , HOZOJI HIROSHI , TSUYUNO NOBUTAKE , NAKATSU KINYA , TOKUYAMA TAKESHI , MATSUSHITA AKIRA , TAKAGI YUSUKE
IPC分类号： H01L25/07 , H01L23/40 , H01L25/18
CPC分类号： H01L23/34 , H01L21/4825 , H01L23/36 , H01L23/4334 , H01L23/473 , H01L23/492 , H01L23/49524 , H01L23/49575 , H01L24/29 , H01L24/33 , H01L24/35 , H01L24/37 , H01L24/40 , H01L24/83 , H01L24/84 , H01L25/072 , H01L25/18 , H01L2224/29111 , H01L2224/32245 , H01L2224/32503 , H01L2224/33 , H01L2224/33181 , H01L2224/3521 , H01L2224/37013 , H01L2224/37124 , H01L2224/37147 , H01L2224/37639 , H01L2224/37644 , H01L2224/37655 , H01L2224/40137 , H01L2224/48091 , H01L2224/4847 , H01L2224/48472 , H01L2224/73265 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/1203 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/351 , H01L2924/00 , H01L2924/1306 , H01L2924/1305 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2924/01047 , H01L2924/01029
摘要： A power semiconductor module includes a power semiconductor element formed with a plurality of control electrodes on one main surface, a first conductor plate bonded by way of a first solder material to one of the main surfaces of the power semiconductor element, and a second conductor plate bonded by way of a second solder material on the other main surface of the power semiconductor element. A first protrusion section protruding from the base section of the applicable first conductor plate and including a first protrusion surface formed over the upper side, is formed over the first conductor plate. A second protrusion section including a second protrusion surface formed facing opposite one of the main surfaces of the power semiconductor element. The first solder material is interposed between the power semiconductor element and the first conductor plate while avoiding the plural control electrodes. If there is an projection from a perpendicular direction by one of the main surfaces of the power semiconductor element, the second protrusion section is formed so that the projecting section on a specified side of the second protrusion surface overlaps the projecting section of the step section formed between the base section of the first conductor plate and the first protrusion section. The plural control electrodes on the power semiconductor element are formed along the specified side of the second protrusion surface.

9. 发明公开

EP3236497A1 SEMICONDUCTOR DEVICE AND METHOD OF STACKING SEMICONDUCTOR DIE FOR SYSTEM-LEVEL ESD PROTECTION 审中-实审
标题翻译：半导体器件和堆叠用于系统级ESD保护的半导体管芯的方法
公开(公告)号：EP3236497A1
公开(公告)日：2017-10-25
申请号：EP17157412.2
申请日：2017-02-22
申请人： Semtech Corporation
发明人： HUANG,, Changjun , CLARK,, Jonathan
IPC分类号： H01L23/60 , H01L21/60 , H01L21/98 , H01L25/065
CPC分类号： H01L25/50 , H01L21/304 , H01L21/561 , H01L21/76898 , H01L21/78 , H01L23/295 , H01L23/3121 , H01L23/3171 , H01L23/481 , H01L23/49575 , H01L23/60 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/85 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L27/0255 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/05548 , H01L2224/05568 , H01L2224/0557 , H01L2224/05573 , H01L2224/0558 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/08146 , H01L2224/08148 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/11849 , H01L2224/11901 , H01L2224/13025 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/14181 , H01L2224/16146 , H01L2224/16227 , H01L2224/16245 , H01L2224/17181 , H01L2224/2929 , H01L2224/32145 , H01L2224/32245 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48247 , H01L2224/48463 , H01L2224/48465 , H01L2224/4847 , H01L2224/73253 , H01L2224/73257 , H01L2224/80203 , H01L2224/8082 , H01L2224/80895 , H01L2224/81203 , H01L2224/81815 , H01L2224/8182 , H01L2224/85203 , H01L2224/85205 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/10252 , H01L2924/10253 , H01L2924/10272 , H01L2924/10322 , H01L2924/10324 , H01L2924/10329 , H01L2924/1033 , H01L2924/10335 , H01L2924/1203 , H01L2924/141 , H01L2924/143 , H01L2924/1433 , H01L2924/1434 , H01L2924/1461 , H01L2924/01082 , H01L2224/11 , H01L2224/03 , H01L2224/81 , H01L2224/80 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device having a first semiconductor die (124c,170,198,124b) with a protection circuit (150) and a second semiconductor die (124b, 124,206,124a) with a protection circuit (150) is disposed over the first semiconductor die; where the protection circuits on each semiconductor die are coupled in parallel. The die are stacked and electrically connected in parallel between leadframe (160) first terminal(160a) and second terminal (160b) through an interconnect structure (134a,140a,140b). An encapsulant (162) is deposited around the first semiconductor die, second semiconductor die, and leadframe. Electrical current from an ESD event is routed through each semiconductor die in parallel to a ground voltage node and the semiconductor packages are thus isolated from an ESD event. At least two semiconductor die with protection circuits may be stacked to increase the ESD current discharge capability.
摘要翻译：具有带保护电路（150）的第一半导体管芯（124c，170,198,124b）和具有保护电路（150）的第二半导体管芯（124b，124,206,124a）的半导体器件设置在第一半导体管芯上; 其中每个半导体管芯上的保护电路并联耦合。管芯堆叠并且通过互连结构（134a，140a，140b）并联电连接在引线框架（160）第一端子（160a）和第二端子（160b）之间。在第一半导体管芯，第二半导体管芯和引线框周围沉积密封剂（162）。来自ESD事件的电流通过每个半导体管芯并联到地电压节点，并且半导体封装因此与ESD事件隔离。可以堆叠至少两个具有保护电路的半导体管芯以增加ESD电流放电能力。

10. 发明公开

EP3178110A1 SEMICONDUCTOR MODULE 审中-实审转让
标题翻译：半导体模块
公开(公告)号：EP3178110A1
公开(公告)日：2017-06-14
申请号：EP16784833.2
申请日：2016-10-14
申请人： ABB Schweiz AG
发明人： HARTMANN, Samuel , SCHLAPBACH, Ulrich
IPC分类号： H01L23/49
CPC分类号： H01L24/49 , H01L24/05 , H01L24/06 , H01L24/48 , H01L25/072 , H01L2224/0603 , H01L2224/48137 , H01L2224/48139 , H01L2224/48227 , H01L2224/4846 , H01L2224/49111 , H01L2224/49431 , H01L2224/49433 , H01L2924/00014 , H01L2924/10161 , H01L2924/1203 , H01L2924/13055 , H01L2924/13091 , H01L2924/15787 , H01L2924/19107 , H01L2924/30107 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor module (10), comprises a substrate plate (14); a semiconductor switch chip (22a) and a diode chip (24a) attached to a collector conductor (16) on the substrate plate (14), wherein the diode chip (24a) is electrically connected antiparallel to the semiconductor switch chip (22a); wherein the semiconductor switch chip (22a) is electrically connected via bond wires (28) to an emitter conductor (18) on the substrate plate (14) providing a first emitter current path (50a), which emitter conductor (18) is arranged oppositely to the semiconductor switch chip (22a) with respect to the diode chip (24a); wherein a gate electrode (40a) of the semiconductor switch chip (22a) is electrically connected via a bond wire (28) to a gate conductor (20) on the substrate plate (14) providing a gate current path (54a), which gate conductor (18) is arranged oppositely to the semiconductor switch chip (22a) with respect to the diode chip (24a); and wherein a protruding area (44) of the emitter conductor (18) runs besides the diode chip (24a) towards the first semiconductor switch chip (22a) and the first semiconductor switch chip (22a) is directly connected via a bond wire (28) with the protruding area (44) providing an additional emitter current path (52) running at least partially along the gate current path (54a). The semiconductor switch chip (22a) is a first semiconductor switch chip and the diode chip (24a) is a first diode chip, which are arranged in a first row (42a). The semiconductor module (10) comprises further a second row (42b) of a second semiconductor switch chip (22b) and a second diode chip (24a, 24b) attached to the collector conductor (16), wherein the diode chip (24a, 24b) of each row is electrically connected antiparallel to the semiconductor switch chip (22a, 22b) of the same row and the first and second rows (42a, 42b) are electrically connected in parallel. The first semiconductor switch chip (22a) is arranged besides the second diode chip (24b) and the second semiconductor chip (22b) is arranged besides the first diode chip (24a).
摘要翻译：半导体模块（10）包括基板（14）; （14）上的集电导体（16）附着的半导体开关芯片（22a）和二极管芯片（24a），其中二极管芯片（24a）与半导体开关芯片（22a）反平行地电连接; 其中所述半导体开关芯片（22a）经由接合线（28）电连接到所述衬底板（14）上的发射极导体（18），从而提供第一发射极电流路径（50a），所述发射极导体（18）被相反地布置相对于所述二极管芯片（24a）连接到所述半导体开关芯片（22a）; 其中所述半导体开关芯片（22a）的栅电极（40a）经由接合线（28）电连接到所述衬底板（14）上的栅极导体（20），从而提供栅极电流路径（54a），所述栅极导体（18）相对于二极管芯片（24a）与半导体开关芯片（22a）相对设置; 并且其中所述发射极导体（18）的突出区域（44）在所述二极管芯片（24a）之外朝向所述第一半导体开关芯片（22a）延伸并且所述第一半导体开关芯片（22a）经由接合线（28）直接连接）与凸出区域（44）提供至少部分地沿栅极电流路径（54a）延伸的额外的发射极电流路径（52）。半导体开关芯片（22a）是第一半导体开关芯片，而二极管芯片（24a）是第一二极管芯片，其布置在第一行（42a）中。所述半导体模块（10）还包括附接到所述集电导体（16）的第二半导体开关芯片（22b）和第二二极管芯片（24a，24b）的第二行（42b），其中所述二极管芯片（24a，24b ）与同一行的半导体开关芯片（22a，22b）反平行地电连接，并且第一和第二行（42a，42b）并联电连接。第一半导体开关芯片（22a）布置在第二二极管芯片（24b）的旁边，第二半导体芯片（22b）布置在第一二极管芯片（24a）的旁边。

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