专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP3176818A4 WIRING BOARD, ELECTRONIC DEVICE, AND ELECTRONIC MODULE 有权
公开(公告)号：EP3176818A4
公开(公告)日：2018-05-02
申请号：EP15826384
申请日：2015-07-23
申请人： KYOCERA CORP
发明人： MORITA YUKIO
IPC分类号： H01L23/498 , H01L21/48 , H01L23/13 , H01L33/48
CPC分类号： H01L23/49838 , H01L21/4846 , H01L23/13 , H01L23/24 , H01L23/49805 , H01L23/49827 , H01L23/49866 , H01L24/32 , H01L24/48 , H01L33/486 , H01L2224/13144 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48157 , H01L2224/48227 , H01L2224/73257 , H01L2224/73265 , H01L2924/00014 , H01L2924/01028 , H01L2924/01079 , H01L2924/1515 , H01L2924/15738 , H01L2924/181 , H05K1/11 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
摘要： A wiring board (1) according to the present invention includes: an insulating base (11) including a main face, a side face, and a notch portion (12) opened in the main face and the side face; and an inner-face electrode (13) disposed on the inner face of the notch portion (12) and to be connected to an external circuit board (5a) with solder (6) therebetween. In such a wiring board (1), the inner-face electrode (13) contains nickel and gold at a surface portion thereof, more nickel than gold at a surface in an outer periphery section (13a), and more gold than nickel at a surface in an inner region.

2. 发明授权

EP3118892B1 LAMINATED SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：层压半导体集成电路器件
公开(公告)号：EP3118892B1
公开(公告)日：2018-05-02
申请号：EP14885109.0
申请日：2014-12-26
申请人： Thruchip Japan Inc.
发明人： KURODA, Tadahiro
IPC分类号： H01L21/48 , H01L21/768 , H01L23/48 , H01L23/538 , H01L23/64 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/06 , H01L27/092
CPC分类号： H01L25/0652 , H01L21/486 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L23/645 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/18 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L27/0688 , H01L27/092 , H01L2221/68327 , H01L2221/6834 , H01L2224/02372 , H01L2224/02375 , H01L2224/02377 , H01L2224/02379 , H01L2224/03002 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/0557 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/08146 , H01L2224/16145 , H01L2224/16227 , H01L2224/16238 , H01L2224/17181 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73257 , H01L2224/80006 , H01L2224/80203 , H01L2224/8083 , H01L2224/80986 , H01L2224/81005 , H01L2224/9202 , H01L2224/92125 , H01L2224/9222 , H01L2224/92225 , H01L2224/92227 , H01L2224/94 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06565 , H01L2924/00014 , H01L2924/13091 , H01L2924/14 , H01L2924/1434 , H01L2924/19107 , H01L2224/80 , H01L2224/03 , H01L2924/00 , H01L2224/80001 , H01L2224/83 , H01L2224/85 , H01L2224/81 , H01L2924/20752
摘要： The invention relates to a multilayer semiconductor integrated circuit device which is provided with a smaller space for a three-dimensional multilayer configuration at a lower cost and with a sufficient power supply quality. A first semiconductor integrated circuit device is provided with a first penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the first power supply potential, and a second penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the second power supply potential. A second semiconductor integrated circuit device having a first electrode and a second electrode is layered on top of the first semiconductor integrated circuit device so that the first electrode and the second electrode are respectively connected to the first penetrating semiconductor region and the second penetrating semiconductor region.

3. 发明公开

EP2731133A3 Interconnection structure and fabrication thereof 审中-公开
标题翻译：互连结构及其制造
公开(公告)号：EP2731133A3
公开(公告)日：2017-11-01
申请号：EP13191022.6
申请日：2013-10-31
申请人： Delta Electronics, Inc.
发明人： Tsai, Hsin-Chang , Lee, Chia-Yen , Lee, Peng-Hsin
IPC分类号： H01L23/48 , H01L21/768 , H01L21/60 , H01L23/485
CPC分类号： H01L21/76898 , H01L21/268 , H01L21/2885 , H01L21/76834 , H01L21/76879 , H01L21/76895 , H01L23/481 , H01L23/49562 , H01L23/49575 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/91 , H01L25/074 , H01L25/18 , H01L25/50 , H01L2224/02372 , H01L2224/0332 , H01L2224/0401 , H01L2224/05009 , H01L2224/05147 , H01L2224/05548 , H01L2224/05557 , H01L2224/0557 , H01L2224/06181 , H01L2224/13024 , H01L2224/131 , H01L2224/13147 , H01L2224/16146 , H01L2224/16147 , H01L2224/16148 , H01L2224/16238 , H01L2224/17181 , H01L2224/73221 , H01L2224/73255 , H01L2224/73257 , H01L2224/81193 , H01L2224/81815 , H01L2924/00014 , H01L2924/12042 , H01L2924/13064 , H01L2924/00012 , H01L2224/05599 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： A method of forming an interconnection structure is disclosed, including providing a substrate having a first side and a second side opposite to the first side, forming a via hole through the substrate, wherein the via hole has a first opening in the first side and a second opening in the second side, forming a first pad covering the first opening, and forming a via structure in the via hole subsequent to forming the first pad, wherein the via structure includes a conductive material and is adjoined to the first pad.
摘要翻译：公开了一种形成互连结构的方法，包括：提供具有第一侧和与第一侧相对的第二侧的衬底;形成穿过衬底的过孔;其中过孔在第一侧中具有第一开口; 形成覆盖所述第一开口的第一焊盘;以及在形成所述第一焊盘之后，在所述通孔中形成通孔结构，其中，所述通孔结构包括导电材料并且与所述第一焊盘相邻接。

5. 发明授权

EP2562826B1 Devices having removed aluminum nitride sections 有权
标题翻译：设备已经移除了氮化铝部分
公开(公告)号：EP2562826B1
公开(公告)日：2017-06-28
申请号：EP12181790.2
申请日：2012-08-24
申请人： Palo Alto Research Center Incorporated
发明人： Chua, Christopher L. , Krusor, Brent S. , Wunderer, Thomas , Johnson, Noble M.
IPC分类号： H01L33/00
CPC分类号： H01L33/0079 , H01L2224/48091 , H01L2224/48465 , H01L2224/73257 , Y10T428/24802 , H01L2924/00014

6. 发明公开

EP3118892A1 LAMINATED SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：层压半导体集成电路器件
公开(公告)号：EP3118892A1
公开(公告)日：2017-01-18
申请号：EP14885109.0
申请日：2014-12-26
申请人： Thruchip Japan Inc.
发明人： KURODA, Tadahiro
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0652 , H01L21/486 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L23/645 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/18 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L27/0688 , H01L27/092 , H01L2221/68327 , H01L2221/6834 , H01L2224/02372 , H01L2224/02375 , H01L2224/02377 , H01L2224/02379 , H01L2224/03002 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/0557 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/08146 , H01L2224/16145 , H01L2224/16227 , H01L2224/16238 , H01L2224/17181 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73257 , H01L2224/80006 , H01L2224/80203 , H01L2224/8083 , H01L2224/80986 , H01L2224/81005 , H01L2224/9202 , H01L2224/92125 , H01L2224/9222 , H01L2224/92225 , H01L2224/92227 , H01L2224/94 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06565 , H01L2924/00014 , H01L2924/13091 , H01L2924/14 , H01L2924/1434 , H01L2924/19107 , H01L2224/80 , H01L2224/03 , H01L2924/00 , H01L2224/80001 , H01L2224/83 , H01L2224/85 , H01L2224/81 , H01L2924/20752
摘要： The invention relates to a multilayer semiconductor integrated circuit device which is provided with a smaller space for a three-dimensional multilayer configuration at a lower cost and with a sufficient power supply quality. A first semiconductor integrated circuit device is provided with a first penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the first power supply potential, and a second penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the second power supply potential. A second semiconductor integrated circuit device having a first electrode and a second electrode is layered on top of the first semiconductor integrated circuit device so that the first electrode and the second electrode are respectively connected to the first penetrating semiconductor region and the second penetrating semiconductor region.
摘要翻译：本发明涉及一种多层半导体集成电路器件，其以较低的成本和足够的电源质量为三维多层结构提供较小的空间。第一半导体集成电路器件设置有第一贯穿半导体区域和第二贯穿半导体区域，第一贯穿半导体区域在厚度方向上贯穿第一半导体本体并且连接到第一电源电位，第二贯穿半导体区域贯穿第一半导体本体厚度方向并且连接到第二电源电位。具有第一电极和第二电极的第二半导体集成电路器件层叠在第一半导体集成电路器件的顶部上，使得第一电极和第二电极分别连接到第一穿透半导体区域和第二穿透半导体区域。

7. 发明公开

EP2884535A3 Packaging DRAM and SOC in an IC package 审中-公开
标题翻译：在IC封装DRAM和SOC的包装
公开(公告)号：EP2884535A3
公开(公告)日：2015-07-22
申请号：EP15150023.8
申请日：2012-08-22
申请人： Marvell World Trade Ltd.
发明人： Sutardja, Sehat
IPC分类号： H01L25/18 , H01L23/498 , H01L21/60 , H01L25/065 , H01L25/10 , H01L23/13
CPC分类号： H01L23/5384 , H01L23/13 , H01L23/34 , H01L23/49838 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/105 , H01L25/18 , H01L27/108 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/4824 , H01L2224/73207 , H01L2224/73215 , H01L2224/73257 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2225/1094 , H01L2924/00014 , H01L2924/014 , H01L2924/14 , H01L2924/1436 , H01L2924/15151 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/30107 , H01L2924/00012 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package comprises a first memory die (458-1) having a first set of connections, a second memory die (458-2) arranged adjacent to the first memory die, the second memory die having a second set of connections, a first substrate (470) having a first opening (472-1) and a second opening (472-2), the first substrate having a third set of connections to connect (474-1) to the first set of connections of the first memory die via the first opening and a fourth set of connections to connect (474-2) to the second set of connections of the second memory die via the second opening, and a second substrate (456) having a first integrated circuit (454) disposed thereon. The first substrate is connected (460-2) to the second substrate with the first integrated circuit disposed between the first substrate and second substrate.

8. 发明公开

EP2880683A1 BVA INTERPOSER 审中-公开
公开(公告)号：EP2880683A1
公开(公告)日：2015-06-10
申请号：EP13826185.4
申请日：2013-08-02
申请人： Invensas Corporation
发明人： CASKEY, Terrence , MOHAMMED, Ilyas , UZOH, Cyprian, Emeka , WOYCHIK, Charles , NEWMAN, Michael , MONADGEMI, Pezhman , CO, Reynaldo , CHAU, Ellis , HABA, Belgacem
IPC分类号： H01L23/48 , H01L23/12
CPC分类号： H01L25/105 , H01L21/486 , H01L23/3114 , H01L23/49811 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/05 , H01L24/45 , H01L24/48 , H01L25/0655 , H01L2224/02379 , H01L2224/04042 , H01L2224/16225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45664 , H01L2224/48091 , H01L2224/48108 , H01L2224/48227 , H01L2224/73207 , H01L2224/73257 , H01L2225/1023 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/381 , H05K1/0298 , H05K3/46 , Y10T29/49126 , Y10T29/49162 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.
摘要翻译：一种制造内插器的方法包括形成结合到第一元件的一个或多个第一表面的多个引线键合。电介质封装形成为接触将相邻的引线键彼此分开的引线键合的边缘表面。进一步的处理包括去除第一元件的至少部分，其中插入件具有通过至少封装彼此分开的第一和第二相对侧，并且插入件分别在第一和第二相对侧具有第一触点和第二触点，用于分别与第一和第二组件电连接，第一触点通过线键合与第二触点电连接。

9. 发明公开

EP2803983A1 Infrared non-destructive inspection method and apparatus 审中-公开
标题翻译： Infrarot-Verfahren und -Vorrichtung zurzerstörungsfreienPrüfung
公开(公告)号：EP2803983A1
公开(公告)日：2014-11-19
申请号：EP14166408.6
申请日：2014-04-29
申请人： JTEKT CORPORATION
发明人： Matsumoto, Naoki , Yoshida, Kouya
IPC分类号： G01N25/72
CPC分类号： G01J5/0896 , G01J1/42 , G01N25/72 , H01L2224/48472 , H01L2224/73257 , H01L2224/859
摘要： In an optical non-destructive inspection method and an optical non-destructive inspection apparatus which can perform inspection accurately in a short time, a measurement object is heated with a laser beam without destroying the measurement object, and a state of the measurement object is determined based on a curve shape of a temperature rise characteristic of the measurement object. In the method and the apparatus, a heating laser beam source (21), at least one infrared detector (31, 32), a control unit (50), and a storage unit (60) are used. The storage unit (60) stores a parameter state-time constant characteristic in which a parameter corresponding to a state of the measurement object is correlated with a time constant indicating the curve shape of the temperature rise characteristic that varies depending on the state of the parameter. The control unit (50) determines the time constant based on the curve shape of the temperature rise characteristic, which extends from a heating start time point to a time point at which a saturated temperature is reached, and determines the state of the parameter of the measurement object based on the determined time constant and the parameter state-time constant characteristic.
摘要翻译：在能够在短时间内精确地进行检查的光学非破坏性检查方法和光学非破坏性检查装置中，用激光束加热测量对象而不破坏测量对象，并且确定测量对象的状态基于测量对象的温度上升特性的曲线形状。在该方法和装置中，使用加热激光束源（21），至少一个红外检测器（31,32），控制单元（50）和存储单元（60）。存储单元（60）存储参数状态 - 时间常数特性，其中与测量对象的状态相对应的参数与指示根据参数的状态而变化的温度上升特性的曲线形状的时间常数相关联。控制单元（50）基于从加热开始时刻到达达到饱和温度的时间点的温度上升特性的曲线形状来确定时间常数，并且确定基于确定的时间常数和参数状态 - 时间常数特征的测量对象。

10. 发明公开

EP2764513A2 STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE 有权
标题翻译：颈部尽量减少接收设备的复制组，无需接线债券，封装基板
公开(公告)号：EP2764513A2
公开(公告)日：2014-08-13
申请号：EP12791306.9
申请日：2012-09-26
申请人： Invensas Corporation
发明人： CRISP, Richard, Dewitt , ZOHNI, Wael , HABA, Belgacem , LAMBRECHT, Frank
IPC分类号： G11C5/04 , G11C5/06 , H01L23/31 , H01L23/34 , H01L23/498 , H01L23/538 , H01L23/00 , H01L25/065 , H01L25/18
CPC分类号： H01L25/0655 , G11C5/04 , G11C5/063 , H01L23/13 , H01L23/3128 , H01L23/49838 , H01L23/50 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/73 , H01L24/92 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/02375 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/0557 , H01L2224/06155 , H01L2224/06156 , H01L2224/06181 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/48145 , H01L2224/73204 , H01L2224/73207 , H01L2224/73209 , H01L2224/73257 , H01L2224/9202 , H01L2225/06506 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06562 , H01L2225/06565 , H01L2225/06589 , H01L2924/00014 , H01L2924/01322 , H01L2924/1431 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/1438 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/3011 , H01L2924/00 , H01L2224/05552 , H01L2924/00012
摘要： A microelectronic assembly 200 can include a circuit panel 154 and first and second microelectronic packages 100A, 100B mounted to respective first and second surfaces 150, 152 of the circuit panel. Each package 100 can include a microelectronic element 101, a substrate 102 having first and second surfaces 108, 110, and terminals 104 exposed at the second surface. The terminals 104 can have a plurality of first terminals including first and second sets 114, 124 thereof disposed on respective first and second opposite sides of a theoretical axis 132. The first terminals 104 can be configured to carry address information usable by circuitry within the package 100 to determine an addressable memory location from among all the available addressable memory locations of a memory storage array of the microelectronic element 101. Signal assignments of the first terminals 104 in the first set 114 can be a mirror image of signal assignments of the first terminals in the second set 124.
摘要翻译：一种微电子封装100包括微电子元件具有存储器存储阵列101。一个102个衬底的表面110上的终端104被配置为在外部部件连接到。衬底接触121在相对的表面曝光的衬底102表面的108和接合至所述微电子元件的元件触点111 101.终端可以包括第一端子104在第一和第二组内的位置布置114,124其设置在respectivement相反的理论轴线132。每个第一端子组104的两侧可以是被配置成承载由微电子封装100内的电路可用于在存储器storageArray寻址存储器位置的确定性矿地址信息。在第一组114中的第一端子104的信号分配可以是第一终端的信号分配的镜像在第二盘124

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式