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    • 3. 发明公开
    • SEMICONDUCTOR DEVICE
    • EP4333078A1
    • 2024-03-06
    • EP22907078.4
    • 2022-11-07
    • Fuji Electric Co., Ltd.
    • KINOSHITA, Akimasa
    • H01L29/78H01L29/12
    • N + -type source regions (4), low-concentration regions (5), and p ++ -type contact regions (6) are each selectively provided in surface regions of a semiconductor substrate (30), at a front surface thereof, and are in contact with a source electrode. The n + -type source regions (4) and the low-concentration regions (5) are in contact with a gate insulating film (8) at sidewalls of a trench (7) and are adjacent to channel portions of a p-type base region, in a depth direction (Z). The p ++ -type contact regions (6) are disposed apart from the trench (7). In surface regions of an epitaxial layer (33) constituting the p-type base region, portions left free of the n + -type source regions (4) and the p ++ -type contact regions (6) configure the low-concentration regions (5) of an n - -type or a p - -type. The low-concentration regions (5) are disposed periodically along the sidewalls of the trench (7), between the trench (7) and the p ++ -type contact regions (6). By the described structure, short-circuit withstand capability may be increased without increasing the number of processes.