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1. 发明公开

EP3161875A1 THROUGH SILICON VIA BASED PHOTOVOLTAIC CELL 审中-公开
标题翻译：通过基于硅通孔的光伏电池
公开(公告)号：EP3161875A1
公开(公告)日：2017-05-03
申请号：EP14896213.7
申请日：2014-06-27
申请人： Intel Corporation
发明人： PHOA, Kinyip , NIDHI, Nidhi , JAN, Chia-Hong , HAFEZ, Walid M. , CHEN, Yi Wei
IPC分类号： H01L31/042 , H01L31/18
CPC分类号： H01L31/022458 , H01L31/022475 , H01L31/028 , H01L31/047 , H01L31/0516 , H01L31/056 , H01L31/068 , H01L31/0682 , H01L31/1884 , H02S40/38 , Y02E10/52 , Y02E10/547
摘要： An embodiment includes an apparatus comprising: a first photovoltaic cell; a first through silicon via (TSV) included in the first photovoltaic cell and passing through at least a portion of a doped silicon substrate, the first TSV comprising (a)(i) a first sidewall, which is doped oppositely to the doped silicon substrate, and (a)(ii) a first contact substantially filling the first TSV; and a second TSV included in the first photovoltaic cell and passing through at least another portion of the doped silicon substrate, the second TSV comprising (b)(i) a second sidewall, which comprises the doped silicon substrate, and (b)(ii) a second contact substantially filling the second TSV; wherein the first and second contacts each include a conductive material that is substantially transparent. Other embodiments are described herein.
摘要翻译：一个实施例包括一种装置，包括：第一光伏电池; 包括在所述第一光伏电池中并且穿过掺杂硅衬底的至少一部分的第一硅通孔（TSV），所述第一硅通孔包括（a）（i）第一侧壁，所述第一侧壁与所述掺杂硅衬底相反地掺杂（a）（ii）基本填充第一TSV的第一接触; 以及包括在所述第一光伏电池中并且穿过所述掺杂硅基板的至少另一部分的第二TSV，所述第二TSV包括（b）（i）包括所述掺杂硅基板的第二侧壁，以及（b）（ii））基本上填充第二TSV的第二触点; 其中所述第一接触件和所述第二接触件各自包括基本透明的导电材料。这里描述了其他实施例。

2. 发明公开

EP3158586A1 MONOLITHIC INTEGRATION OF HIGH VOLTAGE TRANSISTORS&LOW VOLTAGE NON-PLANAR TRANSISTORS 审中-公开
标题翻译：印度尼西亚联邦议会选举委员会
公开(公告)号：EP3158586A1
公开(公告)日：2017-04-26
申请号：EP14895422.5
申请日：2014-06-20
申请人： Intel Corporation
发明人： PHOA, Kinyip , NIDHI, Nidhi , JAN, Chia-Hong , CHANG, Ting
IPC分类号： H01L29/78 , H01L21/335
CPC分类号： H01L29/7834 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823456 , H01L21/823462 , H01L27/0886 , H01L27/0922 , H01L27/0924 , H01L29/0684 , H01L29/0847 , H01L29/66621 , H01L29/7835
摘要： High voltage transistors spanning multiple non-planar semiconductor bodies, such as fins or nanowires, are monolithically integrated with non-planar transistors utilizing an individual non-planar semiconductor body. The non-planar FETs may be utilized for low voltage CMOS logic circuitry within an IC, while high voltage transistors may be utilized for high voltage circuitry within the IC. A gate stack may be disposed over a high voltage channel region separating a pair of fins with each of the fins serving as part of a source/drain for the high voltage device. The high voltage channel region may be a planar length of substrate recessed relative to the fins. A high voltage gate stack may use an isolation dielectric that surrounds the fins as a thick gate dielectric. A high voltage transistor may include a pair of doped wells formed into the substrate that are separated by the high voltage gate stack with one or more fin encompassed within each well.
摘要翻译：跨越多个非平面半导体器件（例如鳍片或纳米线）的高电压晶体管与使用单个非平面半导体器件的非平面晶体管单片集成。非平面FET可用于IC内的低电压CMOS逻辑电路，而高电压晶体管可用于IC内的高电压电路。栅极堆叠可以设置在高压沟道区域上，该高压沟道区域分隔一对翅片，每个翅片用作高压设备的源极/漏极的一部分。高电压通道区域可以是相对于散热片凹进的基板的平面长度。高压栅极堆叠可以使用围绕散热片的隔离电介质作为厚栅极电介质。高压晶体管可以包括形成在衬底中的一对掺杂阱，其被高电压栅极堆叠分隔开，其中一个或多个鳍包围在每个阱内。

3. 发明公开

EP3311400A1 VERTICAL TRANSISTOR USING A THROUGH SILICON VIA GATE 有权
标题翻译：垂直晶体管，采用硅通孔栅
公开(公告)号：EP3311400A1
公开(公告)日：2018-04-25
申请号：EP15895835.5
申请日：2015-06-19
申请人： Intel Corporation
发明人： YANG, Xiaodong , LIN, Jui-Yen , PHOA, Kinyip , NIDHI, Nidhi , CHEN, Yi Wei , SHIH, Kun-huan , HAFEZ, Walid M. , TSAI, Curtis
IPC分类号： H01L21/60
CPC分类号： H01L29/7813 , H01L23/481 , H01L29/0653 , H01L29/66734 , H01L29/7809 , H01L29/945
摘要： A vertical transistor is described that uses a through silicon via as a gate. In one example, the structure includes a substrate, a via in the substrate, the via being filled with a conductive material and having a dielectric liner, a deep well coupled to the via, a drain area coupled to the deep well having a drain contact, a source area between the drain area and the via having a source contact, and a gate contact over the via.

4. 发明公开

EP3158587A1 EXTENDED-DRAIN STRUCTURES FOR HIGH VOLTAGE FIELD EFFECT TRANSISTORS 有权
标题翻译：高压场效应晶体管的扩展漏极结构
公开(公告)号：EP3158587A1
公开(公告)日：2017-04-26
申请号：EP14895454.8
申请日：2014-06-18
申请人： Intel Corporation
发明人： NIDHI, Nidhi , JAN, Chia-Hong , HAFEZ, Walid
IPC分类号： H01L29/78 , H01L21/335
CPC分类号： H01L29/402 , H01L21/26513 , H01L23/66 , H01L29/1083 , H01L29/401 , H01L29/404 , H01L29/408 , H01L29/42368 , H01L29/42376 , H01L29/4983 , H01L29/66545 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： Planar and non-planar field effect transistors with extended-drain structures, and techniques to fabricate such structures. In an embodiment, a field plate electrode is disposed over an extended-drain, with a field plate dielectric there between. The field plate is disposed farther from the transistor drain than the transistor gate. In a further embodiment, an extended-drain transistor has source and drain contact metal at approximately twice a pitch, of the field plate and the source and/or drain contact metal. In a further embodiment, an isolation dielectric distinct from the gate dielectric is disposed between the extended-drain and the field plate. In a further embodiment, the field plate may be directly coupled to one or more of the transistor gate electrode or a dummy gate electrode without requiring upper level interconnection. In an embodiment, a deep well implant may be disposed between a lightly-doped extended-drain and a substrate to reduce drain-body junction capacitance and improve transistor performance.
摘要翻译：具有扩展漏极结构的平面和非平面场效应晶体管以及制造这种结构的技术。在一个实施例中，场板电极设置在延伸漏极之上，其间具有场板电介质。场板设置得比晶体管栅极更远离晶体管的漏极。在进一步的实施例中，延伸漏极晶体管具有场板和源极和/或漏极接触金属的大约两倍节距的源极和漏极接触金属。在另一个实施例中，在延伸漏极和场板之间设置与栅极电介质不同的隔离电介质。在另一实施例中，场板可以直接耦合到晶体管栅极电极或伪栅极电极中的一个或多个，而不需要上层互连。在一个实施例中，深阱注入可以设置在轻掺杂的延伸漏极和衬底之间以减小漏极 - 本体结电容并改善晶体管性能。

5. 发明公开

EP3836202A1 NANORIBBON THICK GATE DEVICES WITH DIFFERENTIAL RIBBON SPACING AND WIDTH FOR SOC APPLICATIONS 审中-公开
公开(公告)号：EP3836202A1
公开(公告)日：2021-06-16
申请号：EP20193557.4
申请日：2020-08-31
申请人： Intel Corporation
发明人： TRIVEDI, Tanuj , RAMASWAMY, Rahul , KIM, Jeong Dong , CHANG, Ting , HAFEZ, Walid M. , FALLAHAZAD, Babak , CHANG, Hsu-Yu , NIDHI, Nidhi
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/06
摘要： Embodiments disclosed herein include nanowire and nanoribbon devices with non-uniform dielectric thicknesses. The semiconductor device comprises a substrate (106) and a plurality of first semiconductor layers (110A) in a vertical stack over the substrate. The first semiconductor layers have a first spacing (SA). A first dielectric (115A) surrounds each of the first semiconductor layers, and the first dielectric has a first thickness (TDA). The semiconductor device further comprises a plurality of second semiconductor layers (110B) in a vertical stack over the substrate, where the second semiconductor layers may have a second spacing (SB) that is greater than the first spacing. A second dielectric (115B) surrounds each of the second semiconductor layers, and the second dielectric has a second thickness (TDB) that is greater than the first thickness.

6. 发明公开

EP3311401A1 ON-CHIP THROUGH-BODY-VIA CAPACITORS AND TECHNIQUES FOR FORMING SAME 审中-实审
标题翻译：芯片上通过身体威盛电容器和形成相同的技术
公开(公告)号：EP3311401A1
公开(公告)日：2018-04-25
申请号：EP15896494.0
申请日：2015-06-22
申请人： Intel Corporation
发明人： CHEN, Yi Wei , PHOA, Kinyip , NIDHI, Nidhi , LIN, Jui-Yen , SHIH, Kun-Huan , YANG, Xiaodong , HAFEZ, Walid M. , TSAI, Curtis
IPC分类号： H01L21/60
CPC分类号： H01L23/481 , H01L21/76831 , H01L21/76898 , H01L27/0629 , H01L27/1203 , H01L28/90 , H01L29/945
摘要： Techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a semiconductor layer, and a dielectric layer may be formed between the TBV and the surrounding semiconductor layer. The TBV may serve as one electrode (e.g., anode) of a TBV capacitor, and the dielectric layer may serve as the dielectric body of that TBV capacitor. In some embodiments, the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor. To that end, in some embodiments, the entire semiconductor layer may comprise a low-resistivity material, whereas in some other embodiments, low-resistivity region(s) may be provided just along the sidewalls local to the TBV, for example, by selective doping in those location(s). In other embodiments, a conductive layer formed between the dielectric layer and the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor.

7. 发明公开

EP3836203A1 LONG CHANNEL NANOWIRE TRANSISTORS FOR SOC APPLICATIONS 审中-公开
公开(公告)号：EP3836203A1
公开(公告)日：2021-06-16
申请号：EP20197831.9
申请日：2020-09-23
申请人： INTEL Corporation
发明人： RAMASWAMY, Rahul , HAFEZ, Walid M. , NIDHI, Nidhi , CHANG, Ting , CHANG, Hsu-Yu , TRIVEDI, Tanuj , KIM, Jeong Dong , FALLAHAZAD, Babak
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/775 , H01L29/78 , H01L27/092 , H01L21/8238
摘要： Embodiments disclosed herein include nanoribbon and nanowire semiconductor devices. In an embodiment, the semiconductor device comprises a nanowire disposed above a substrate. In an embodiment, the nanowire has a first dopant concentration, and the nanowire comprises a pair of tip regions on opposite ends of the nanowire. In an embodiment, the tip regions comprise a second dopant concentration that is greater than the first dopant concentration. In an embodiment, the semiconductor device further comprises a gate structure over the nanowire. In an embodiment, the gate structure is wrapped around the nanowire, and the gate structure defines a channel region of the device. In an embodiment, a pair of source/drain regions are on opposite sides of the gate structure, and both source/drain regions contact the nanowire.

8. 发明公开

EP3161872A1 MULTI-GATE TRANSISTOR WITH VARIABLY SIZED FIN 有权转让
标题翻译：多门式晶体管麻醉机变压器RIPEM
公开(公告)号：EP3161872A1
公开(公告)日：2017-05-03
申请号：EP14896232.7
申请日：2014-06-27
申请人： Intel Corporation
发明人： NIDHI, Nidhi , JAN, Chia-Hong , OLAC-VAW, Roman W. , CHANG, Hsu-Yu , DIAS, Neville L. , HAFEZ, Walid M. , RAMASWAMY, Rahul
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823412 , H01L21/26586 , H01L21/823418 , H01L21/823431 , H01L27/0886 , H01L29/0847 , H01L29/1037 , H01L29/42368 , H01L29/785 , H01L29/7851 , H01L29/7856
摘要： An embodiment includes an apparatus comprising: a non-planar transistor comprising a fin, the fin including a source region having a source region width and a source region height, a channel region having a channel region width and a channel region height, a drain region having a drain width and a drain height, and a gate dielectric formed on a sidewall of the channel region; wherein the apparatus includes at least one of (a) the channel region width being wider than the source region width, and (b) the gate dielectric including a first gate dielectric thickness at a first location and a second gate dielectric thickness at a second location, the first and second locations located at an equivalent height on the sidewall and the first and second gate dielectrics thicknesses being unequal to one another. Other embodiments are described herein.
摘要翻译：一个实施例包括一种装置，包括：非平面晶体管，包括鳍片，所述鳍片包括源极区域宽度和源极区域高度的源极区域，具有沟道区域宽度和沟道区域高度的沟道区域，漏极区域具有漏极宽度和漏极高度，以及形成在沟道区域的侧壁上的栅极电介质; 其中所述装置包括以下中的至少一个：（a）所述沟道区宽度宽于所述源极区宽度，以及（b）所述栅极电介质包括在第一位置处的第一栅极电介质厚度和在第二位置处的第二栅极电介质厚度位于侧壁上的等效高度的第一和第二位置以及第一和第二栅极电介质厚度彼此不相等。本文描述了其它实施例。

9. 发明公开

EP4024474A2 EXTENDED-DRAIN STRUCTURES FOR HIGH VOLTAGE FIELD EFFECT TRANSISTORS 审中-公开
公开(公告)号：EP4024474A2
公开(公告)日：2022-07-06
申请号：EP22154453.9
申请日：2014-06-18
申请人： INTEL Corporation
发明人： NIDHI, Nidhi , JAN, Chia-Hong , HAFEZ, Walid
IPC分类号： H01L29/78 , H01L21/336 , H01L29/40
摘要： Planar and non-planar field effect transistors with extended-drain structures, and techniques to fabricate such structures. In an embodiment, a field plate electrode is disposed over an extended-drain, with a field plate dielectric there between. The field plate is disposed farther from the transistor drain than the transistor gate. In a further embodiment, an extended-drain transistor has source and drain contact metal at approximately twice a pitch, of the field plate and the source and/or drain contact metal. In a further embodiment, an isolation dielectric distinct from the gate dielectric is disposed between the extended-drain and the field plate. In a further embodiment, the field plate may be directly coupled to one or more of the transistor gate electrode or a dummy gate electrode without requiring upper level interconnection. In an embodiment, a deep well implant may be disposed between a lightly-doped extended-drain and a substrate to reduce drain-body junction capacitance and improve transistor performance.

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