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1. 发明公开

EP2665225A4 BIT GENERATION DEVICE AND BIT GENERATION METHOD 有权
标题翻译： BIT-ERZEUGUNGSVORRICHTUNG UND BIT-ERZEUGUNGSVERFAHREN
公开(公告)号：EP2665225A4
公开(公告)日：2017-04-26
申请号：EP11855851
申请日：2011-01-13
申请人： MITSUBISHI ELECTRIC CORP
发明人： SHIMIZU KOICHI , SUZUKI DAISUKE , KASUYA TOMOMI
IPC分类号： H04L9/10
CPC分类号： H03K3/02 , G09C1/00 , H03K5/1252 , H03K19/003 , H03K19/00361 , H04L9/3278
摘要： A bit generation apparatus 100 is provided with a glitch generation circuit 120 that generates glitch signals y1 to yM which include a plurality of pulses, and T-FF bit generation circuits 131(1) to 131(M) which input the glitch signals y1 to yM, and based on either rising edges or falling edges of the plurality of pulses included in the glitch signals, generate a bit value of either 0 or 1. Each of the T-FF bit generation circuits 131(1) to 131(M) generates a respective bit value b1 to bM based on either the parity of the number of rising edges or the parity of the number of falling edges of the plurality of pulses. As a result of employment of the T-FF bit generation circuits 131(1) to 131(M), circuits that are conventionally required but not essential for the glitch PUF become unnecessary. This serves to prevent expansion in circuit scale and increase in processing time of bit generation for the bit generation circuit 100.
摘要翻译：位生成装置100具备：生成包含多个脉冲的毛刺信号y1〜yM的毛刺生成电路120，以及将毛刺信号y1〜yM输入到生成电路130的T-FF位生成电路131（1）〜131（M） yM，并且基于在毛刺信号中包括的多个脉冲的上升沿或下降沿，产生0或1的比特值。每个T-FF比特产生电路131（1）至131（M）基于多个脉冲的上升沿的数量的奇偶性或下降沿的数量的奇偶性来生成相应的比特值b1至bM。作为T-FF比特生成电路131（1）至131（M）的使用结果，传统上需要但不是毛刺PUF所必需的电路变得不必要。这用于防止比特生成电路100的电路规模的扩大和比特生成的处理时间的增加。

2. 发明公开

EP3014768A4 DELAY CIRCUIT INDEPENDENT OF SUPPLY VOLTAGE 审中-公开
标题翻译：独立供电延迟电路
公开(公告)号：EP3014768A4
公开(公告)日：2017-02-22
申请号：EP14818603
申请日：2014-06-25
申请人： ESS TECH INC
发明人： MALLINSON A MARTIN
IPC分类号： H03K5/15 , H03H11/26 , H03K5/133 , H03K5/14 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/00315 , H03K5/133 , H03K5/14 , H03K5/15046 , H03K19/00361 , H03K19/00369 , H03K19/018521

3. 发明授权

EP2079162B1 Apparatus and method having reduced flicker noise 有权
标题翻译：装置和方法，具有减少的闪烁噪声
公开(公告)号：EP2079162B1
公开(公告)日：2014-10-01
申请号：EP09000308.8
申请日：2009-01-12
申请人： Intel Mobile Communications GmbH
发明人： Siprak, Domagoj , Tiebout, Marc
IPC分类号： H03D7/14 , H03K19/003 , H03B5/12
CPC分类号： H03K19/00361 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03B2200/0088 , H03D7/1441 , H03D7/1458 , H03D2200/0043 , H03D2200/0084
摘要： Different techniques for signal processing having reduced flicker noise are described herein. A semiconductor circuitry for processing a frequency signal, comprises a field effect transistor. The field effect transistor (100) has a gate terminal (110) for receiving a bias signal and a bulk terminal (112) for receiving a back-bias signal. The semiconductor circuitry further comprises a first circuit portion to provide a alternating bias signal and a second circuit portion to provide a forward back-bias signal.

4. 发明公开

EP2774179A1 BLOCK POWER SWITCH WITH EMBEDDED ELECTROSTATIC DISCHARGE (ESD) PROTECTION AND ADAPTIVE BODY BIASING 有权
标题翻译：随着嵌入式保护静电放电（ESD）和自适应偏置打砖块
公开(公告)号：EP2774179A1
公开(公告)日：2014-09-10
申请号：EP12806731.1
申请日：2012-11-01
申请人： Qualcomm Incorporated
发明人： POPOVICH, Mikhail , PAN, Yuan-cheng Christopher , ANDREEV, Boris , ZHANG, Junmou , JALILIZEINALI, Reza
IPC分类号： H01L27/02 , H02H9/04 , H03K19/003
CPC分类号： H01L27/0251 , H02H9/046 , H03K19/00361 , Y10T29/49105
摘要： A block power switch may be embedded with electrostatic discharge (ESD) protection circuitry. A transistor portion of the block power switch may be allocated to act as part of ESD protection circuitry and may be combined with an RC clamp to provide ESD protection. Adaptive body biasing (ABB) may be applied to the block power switch to reduce on-chip area and decrease leakage current of the block power switch.

5. 发明公开

EP2605401A3 Apparatus and method having reduced flicker noise 审中-公开
标题翻译：装置和方法，具有减少的闪烁噪声
公开(公告)号：EP2605401A3
公开(公告)日：2014-04-30
申请号：EP13153022.2
申请日：2009-01-12
申请人： Intel Mobile Communications GmbH
发明人： Siprak, Domagoj , Tiebout, Marc
IPC分类号： H03F1/26 , H03K19/003 , H03D7/14
CPC分类号： H03K19/00361 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03B2200/0088 , H03D7/1441 , H03D7/1458 , H03D2200/0043 , H03D2200/0084
摘要： An apparatus comprises an active device (403, 405) structured in a semiconductor body and having control terminal (400, 401) adapted to receive a bias signal, and bulk terminal (413, 414) adapted to receive a forward body-bias signal. Further, the apparatus comprises a circuit (412) or a node coupled to the bulk terminal (400, 401) and adapted to provide the forward body-bias signal. A duty cycle of the bias signal and/or a duty cycle of the forward body-bias signal is determined by emission time constants of a trap in the active device (403, 405) in the off state and in the on state of the active device (403, 405).

6. 发明授权

EP0805559B1 Treiberstufe 失效
标题翻译：驱动级
公开(公告)号：EP0805559B1
公开(公告)日：2013-11-27
申请号：EP97106966.1
申请日：1997-04-25
申请人： Infineon Technologies AG
发明人： Sommer, Diether, Dipl.-Phys. , Mitteregger, Gerhard , Savignac, Dominique, Dr.rer.nat. , Mukundarajan, Suraj
IPC分类号： H03K19/003 , H03K19/017 , H03K5/1534
CPC分类号： H03K19/00361

7. 发明公开

EP2487796A3 Output circuit, system including output circuit, and method of controlling output circuit 失效转让
标题翻译：输出电路，包括输出电路的系统以及控制输出电路的方法
公开(公告)号：EP2487796A3
公开(公告)日：2013-07-31
申请号：EP12151757.7
申请日：2012-01-19
申请人： Fujitsu Semiconductor Limited
发明人： Konishi, Kenichi , Miyazaki, Hiroshi
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/018507 , H03K19/00361
摘要： An output circuit (34) includes a first transistor (T1) coupled to an external terminal (P2) and including a gate terminal that receives a first drive signal (S3). The first transistor (T1) drives a potential at the external terminal (P2) in accordance with the first drive signal (S3). A first capacitor (C1) includes a first end coupled to the gate terminal of the first transistor (T1) and a second end coupled to the external terminal (P2). The output circuit (34) also includes a circuit portion (44) coupled to the first transistor (T1). The circuit portion (44) maintains the first transistor (T1) in an inactivated state when the gate terminal of the first transistor (T1) is in a floating state.
摘要翻译：输出电路（34）包括耦合到外部端子（P2）并包括接收第一驱动信号（S3）的栅极端子的第一晶体管（T1）。第一晶体管（T1）根据第一驱动信号（S3）在外部端子（P2）驱动电势。第一电容器（C1）包括耦合到第一晶体管（T1）的栅极端子的第一端和耦合到外部端子（P2）的第二端。输出电路（34）还包括耦合到第一晶体管（T1）的电路部分（44）。当第一晶体管（T1）的栅极端子处于浮置状态时，电路部分（44）将第一晶体管（T1）保持在非激活状态。

8. 发明公开

EP2293448A3 Method and apparatus for an N-nary logic circuit 审中-公开
标题翻译：对于N进制逻辑电路的方法和装置
公开(公告)号：EP2293448A3
公开(公告)日：2011-05-04
申请号：EP10179489.9
申请日：1999-12-10
申请人： Apple Inc.
发明人： Blomgren, James S. , Potter, Terence M. , Horne, Stephen C. , Seningen, Michael R. , Petro, Anthony M.
IPC分类号： H03K19/094 , H03K19/00 , H03K19/096
CPC分类号： G06F1/08 , G06F5/015 , G06F7/02 , G06F7/026 , G06F7/483 , G06F7/49 , G06F7/508 , G06F7/5443 , G06F17/5045 , G06F2207/3824 , G11C7/1006 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/0963 , H03K19/215
摘要： The present invention is a method and apparatus (106) for an N-NARY logic circuit that uses N-NARY signals (A0-A3, B0-B3). The present invention includes a shared logic tree circuit (107) that evaluates one or more N-NARY input signals and produces an N-NARY output signal (V0-V3). The present invention additionally includes a first N-NARY input signal (A0-A3) coupled to the shared logic tree circuit and a second N-NARY input signal (B0-B3) coupled to the shared logic tree circuit. The shared logic circuit evaluates the first and second N-NARY input signal and produces an N-NARY output signal (V0-V3) coupled, which additionally couples to the shared logic tree circuit. The present invention uses signals that include 1 of 2 N-NARY signals, 1 of 3 N-NARY signals, 1 of 4 N-NARY signals (A0-A3, B0-B3), 1 of 8 N-NARY signals, and the general 1 of N N-NARY signals. The present invention evaluates any given function that includes the AND/NAND, OR/NOR, or XOR/Equivalence functions.

9. 发明授权

EP1011197B1 Method for generating differential tri-states and differential tri-state circuit 有权
标题翻译：一种用于产生三态差分和差分三态电路的方法
公开(公告)号：EP1011197B1
公开(公告)日：2009-07-22
申请号：EP99124484.9
申请日：1999-12-08
申请人： NEC Electronics Corporation
发明人： Watarai, Seiichi
IPC分类号： H03K19/094 , H03K19/003 , H03K17/693
CPC分类号： H03K19/09429 , H03K17/693 , H03K19/00361

10. 发明授权

EP1085575B1 Electronic device for controlling the "bouncing" in electronic circuits integrated on semiconductor substrate 有权
标题翻译：用于电子电路的半导体衬底调节集成一个“反弹效应”的电子部件
公开(公告)号：EP1085575B1
公开(公告)日：2008-09-10
申请号：EP99830573.4
申请日：1999-09-13
申请人： STMicroelectronics S.r.l.
发明人： Imbruglia, Antonio , Moscuzza, Sebastiano , Airaksinen, Maria Leena
IPC分类号： H01L27/092 , H01L29/423 , H03K19/003
CPC分类号： H03K19/00361 , H01L27/092 , H01L29/4238 , H03K17/164

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