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1. 发明授权

EP3917008B1 LOW EMISSION ELECTRONIC SWITCH FOR SIGNALS WITH LONG TRANSITION TIMES 有权
公开(公告)号：EP3917008B1
公开(公告)日：2024-07-10
申请号：EP21173082.5
申请日：2021-05-10
IPC分类号： H03K17/16 , H03K19/0185 , H04L25/03
CPC分类号： H03K17/167 , H03K19/00361

2. 发明授权

EP2587672B1 Power switch acceleration scheme for fast wakeup 有权转让
标题翻译：快速唤醒的电源开关加速方案
公开(公告)号：EP2587672B1
公开(公告)日：2018-04-11
申请号：EP12186614.9
申请日：2012-09-28
申请人： APPLE INC.
发明人： Takayanagi, Toshinari , Suzuki, Shingo
IPC分类号： H03K19/00 , H03K19/003 , H03K17/042 , H03K17/16
CPC分类号： H03K17/284 , H03K17/0412 , H03K17/04206 , H03K17/164 , H03K19/0016 , H03K19/00361 , Y10T307/858
摘要： A method and apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit (10) includes at least one power gated circuit block (14A-14C). The power gated circuit block (14A-14C) includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block (14A-14C) is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases,. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block (14A-14C). The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.

3. 发明公开

EP3262760A1 OUTPUT DRIVER WITH BACK-POWERING PREVENTION 审中-公开
标题翻译：输出驱动器，防止反弹
公开(公告)号：EP3262760A1
公开(公告)日：2018-01-03
申请号：EP16705869.2
申请日：2016-01-26
申请人： Qualcomm Incorporated
发明人： CHEN, Wilson Jianbo , TAN, Chiew-Guan , JALILIZEINALI, Reza
IPC分类号： H03K19/003
CPC分类号： H03K17/26 , H03K17/18 , H03K19/00315 , H03K19/00361
摘要： A back-power prevention circuit is provided that protects a buffer transistor from back-power during a back-power condition by charging a signal lead coupled to a gate of the buffer transistor to a pad voltage and by charging a body of the buffer transistor to the pad voltage.

4. 发明公开

EP3205023A1 ADAPTIVE DYNAMIC KEEPER CIRCUIT 审中-公开
标题翻译：自适应动态保持器电路
公开(公告)号：EP3205023A1
公开(公告)日：2017-08-16
申请号：EP15766687.6
申请日：2015-09-03
申请人： Qualcomm Incorporated
发明人： PUCKETT, Joshua Lance , KLEIN, Anthony Dale , VISWANATHAN, Kaushik
IPC分类号： H03K19/003 , H03K19/096
CPC分类号： H03K19/00315 , H03K19/00361 , H03K19/09482 , H03K19/0963
摘要： Aspects disclosed herein describe a keeper circuit that adapts to variations in the fabrication process used to manufacture a dynamic circuit (105). The different characteristics of the circuit elements may cause a keeper circuit (110) to behave in an unintended manner. In one example, a logical state of the dynamic circuit may be erroneously changed because of a strong (i.e., leaky) NMOS transistor (235) in a pull down or discharge path (230). An adaptive keeper circuit (110), however, is designed to prevent such unintended behavior regardless of any change in the characteristics of the circuit elements in the dynamic circuit. The adaptive keeper circuit (110) matches the behavior of the pull down path (230) and prevents the pull down path from erroneously changing the logical state (207) stored by the dynamic circuit (105).
摘要翻译：这里公开的方面描述了适应于用于制造动态电路的制造工艺的变化的保持器电路。电路元件的不同特性可能导致保持器电路以无意的方式行为。在一个示例中，由于下拉或放电路径中的强（即泄漏）NMOS晶体管，动态电路的逻辑状态可能被错误地改变。然而，自适应保持器电路被设计为防止这种无意的行为，而不管动态电路中的电路元件的特性的任何变化。自适应保持器电路匹配下拉路径的行为并防止下拉路径错误地改变由动态电路存储的逻辑状态。

5. 发明公开

EP3166226A1 SLEW CONTROL USING A SWITCHED CAPACITOR CIRCUIT 审中-公开
标题翻译：使用开关电容电路的SLEW控制
公开(公告)号：EP3166226A1
公开(公告)日：2017-05-10
申请号：EP16196651.0
申请日：2016-10-31
申请人： NXP B.V.
发明人： ZHANG, Xu , DELSHADPOUR, Siamak , YAZDI, Ahmad
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0185
CPC分类号： H03K5/01 , H03K3/353 , H03K17/16 , H03K19/00361 , H03K19/018507 , H03K19/018585
摘要： An apparatus includes a swing control circuit, a slew control circuit, and a driver circuit. The swing control circuit is configured and arranged to be powered by an input supply voltage, to receive an input data signal and, in response, to generate a first internal signal having a swing level corresponding to the input supply voltage. The slew control circuit, including a switched capacitor circuit, is configured and arranged to receive the first internal signal and, in response, to generate a second internal signal using the switched capacitor circuit that is configured to set a slew rate for the second internal signal. Further, the driver circuit is configured and arranged to receive the second internal signal and, in response, to generate an output signal that is based upon the swing level and the slew rate of the second internal signal.
摘要翻译：一种装置包括摆动控制电路，摆动控制电路和驱动器电路。摆动控制电路被配置和布置成由输入电源电压供电，以接收输入数据信号，并且作为响应，生成具有对应于输入供电电压的摆动电平的第一内部信号。包括开关电容器电路的摆动控制电路被配置和布置为接收第一内部信号，并且作为响应，使用开关电容器电路生成第二内部信号，该开关电容器电路被配置为设置第二内部信号的转换速率。此外，驱动器电路被配置和布置为接收第二内部信号，并且作为响应，生成基于第二内部信号的摆动电平和摆动速率的输出信号。

6. 发明公开

EP3038099A4 SHIFT REGISTER UNIT AND DRIVING METHOD THEREFOR, SHIFT REGISTER CIRCUIT AND DISPLAY DEVICE 有权
标题翻译：移位寄存器单元，驱动器及其方法，移位寄存器电路及显示装置
公开(公告)号：EP3038099A4
公开(公告)日：2017-02-01
申请号：EP15777857
申请日：2015-03-27
申请人： BOE TECHNOLOGY GROUP CO LTD , BEIJING BOE DISPLAY TECH CO
发明人： YAO SHULIN , LEE SEUNG MIN , SUN ZHIHUA , WU XINGJI , CUI WENHAI , LIU BAOYU
IPC分类号： G09G3/36 , G09G3/3266 , H03K5/1252 , H03K19/003
CPC分类号： G09G3/3648 , G09G3/3258 , G09G3/3266 , G09G3/3677 , G09G2300/04 , G09G2310/0267 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G11C19/28 , H03K19/00361
摘要： The application relates to a shift register unit and a driving method thereof, a shift register circuit and a display apparatus. The shift register unit may include a gate starting terminal, a first clock terminal, a second clock terminal, a reset terminal, a low level terminal, a gate output terminal, a storage capacitor, a charging module, an output control module and a reset module. In the shift register according to the present application, since the reset operation is under control of the second transistor and the fifth transistor both, an improper reset operation will not occur, even if the signal at the reset terminal is unstable.

7. 发明公开

EP2895931A4 LINEAR VOLTAGE REGULATOR BASED ON-DIE GRID 有权
标题翻译：线性电压调节器上的进气格栅上的芯片的基础
公开(公告)号：EP2895931A4
公开(公告)日：2016-06-15
申请号：EP13836853
申请日：2013-06-11
申请人： INTEL CORP
发明人： PAILLET FABRICE , SHOR JOSEPH , GEANNOPOULOS GEORGE L , TAN HONG YUN
IPC分类号： G05F1/56 , G06F1/26 , H03K19/003
CPC分类号： G06F1/26 , G05F1/56 , H03K19/00361
摘要： Described is a linear voltage regulator circuit comprising a first voltage regulator comprising a first source follower having a first node to provide a first power supply, and a second node different from the first node; and a second voltage regulator comprising a second source follower having a first node to provide a second power supply, and a second node different from the first node, wherein the second nodes of the first and second voltage regulators are electrically shorted.

8. 发明公开

EP2693640A1 SERIAL COMMUNICATION DEVICE 有权转让
公开(公告)号：EP2693640A1
公开(公告)日：2014-02-05
申请号：EP12764221.3
申请日：2012-02-24
申请人： Renesas Electronics Corporation
发明人： ISHIZEKI, Yoshiaki
IPC分类号： H03K17/16 , H03K17/687 , H03K19/0175
CPC分类号： H04L25/03885 , H03K17/16 , H03K17/166 , H03K19/00361 , H03K19/017545 , H03K19/018507 , H03K19/018521 , H04L1/20
摘要： A serial communication apparatus includes a slew rate control circuit, an output circuit, a detection circuit, and a switching circuit. The slew rate control circuit has a predetermined impedance, and supplies a constant current from an output according to an input signal. In the output circuit a first capacitance is charged and discharged by the constant current from the slew rate control circuit. The output circuit outputs a digital signal from an output terminal according to a drive voltage. The noise detection circuit detects noise propagated from the output terminal, and outputs a switching signal according to a detection result. The switching circuit switches an impedance of the slew rate control circuit to a value smaller than the predetermined impedance according to the switching signal.

9. 发明公开

EP2675066A1 System and method of providing power using switching circuits 审中-公开
标题翻译：系统和Verfahren zur Leistungsversorgung手套Schaltkreisen
公开(公告)号：EP2675066A1
公开(公告)日：2013-12-18
申请号：EP13184206.4
申请日：2008-12-19
申请人： Qualcomm Incorporated
发明人： Rao, Hari , Chen, Chen , Chaba, Ritu
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H03K19/017581 , H03K19/00361 , Y10T307/438 , Y10T307/461
摘要： In a particular illustrative embodiment, a system is disclosed that includes a first power domain (110) that is responsive to a first power switching circuit (106) and a second power domain (112) that is responsive to a second power switching circuit (108). The system also includes a logic circuit (102) adapted to selectively activate the first power switching circuit (106) and the second power switching circuit (108). At least one of the first power switching circuit and the second power switching circuit includes a first set of transistors (114) adapted for activation during a first power up stage and a second set of transistors (116) adapted for activation during a second power up stage after at least one of the first set of transistors (114) are activated.
摘要翻译：在特定说明性实施例中，公开了一种系统，其包括响应于第一功率切换电路（106）的第一功率域（110）和响应于第二功率切换电路（108）的第二功率域（112））。该系统还包括适于选择性地激活第一功率开关电路（106）和第二功率切换电路（108）的逻辑电路（102）。第一功率开关电路和第二功率开关电路中的至少一个包括适于在第一加电阶段期间激活的第一组晶体管（114）和适于在第二次上电期间激活的第二组晶体管（116）在第一组晶体管（114）中的至少一个被激活之后的阶段。

10. 发明公开

EP2487795A3 Output circuit, system including output circuit, and method of controlling output circuit 失效转让
标题翻译：输出电路系统，用于控制所述输出电路的输出电路和方法
公开(公告)号：EP2487795A3
公开(公告)日：2013-04-24
申请号：EP12151674.4
申请日：2012-01-19
申请人： Fujitsu Semiconductor Limited
发明人： Miyazaki, Hiroshi
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/00361 , H03K19/018507
摘要： An output circuit (34) includes a first transistor (T1) coupled to an external terminal (P2) and having a gate terminal that receives a first drive signal (S5). The first transistor (T1) drives a potential at the external terminal (P2) in accordance with the first drive signal (S5). The output circuit (34) also includes a capacitor (C1). The capacitor (C1) includes a first end coupled to the gate terminal of the first transistor (T1). A clamp circuit (46) clamps a second end of the capacitor (C1) to a potential corresponding to the operation of the first transistor (T1).

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