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1. 发明公开

EP2894679A1 Gallium nitride material devices including backside vias and methods of fabrication 审中-公开
标题翻译： Vorrichtungen aus Galliumnitridmaterial mitrückseitigenKontaktlöchernund Herstellungsverfahren
公开(公告)号：EP2894679A1
公开(公告)日：2015-07-15
申请号：EP15154907.8
申请日：2002-02-22
申请人： International Rectifier Corporation
发明人： Weeks, Warren , Piner, Edwin , Borges, Ricardo , Linthicum, Kevin
IPC分类号： H01L33/00 , H01S5/323 , H01S5/02 , H01L33/38 , H01L29/417 , H01L29/80 , H01L47/02 , H01L29/861 , H01L29/06 , H01L33/32 , H01L29/20
CPC分类号： H01L33/38 , H01L29/0657 , H01L29/2003 , H01L29/417 , H01L29/802 , H01L29/861 , H01L33/0079 , H01L33/32 , H01L33/382 , H01L47/026 , H01L2924/10155
摘要： The invention includes providing gallium nitride material devices having backside vias and methods to form the devices. The devices include a gallium nitride material formed over a substrate, such as silicon. The device also may include one or more non-conducting layers between the substrate and the gallium nitride material which can aid in the deposition of the gallium nitride material. A via is provided which extends from the backside of the device through the non-conducting layer(s) to enable electrical conduction between an electrical contact deposited within the via and, for example, an electrical contact on the topside of the device. Thus, devices of the invention may be vertically conducting. In other cases, the vias may be free of electrical contacts, for example, to enhance light extraction. Exemplary devices include laser diodes (LDs), light emitting diodes (LEDs), power rectifier diodes, FETs (e.g., HFETs), Gunn-effect diodes, and varactor diodes, amongst others.
摘要翻译：本发明包括提供具有背面通孔的氮化镓材料器件和形成器件的方法。这些器件包括在诸如硅之类的衬底上形成的氮化镓材料。该器件还可以包括在衬底和氮化镓材料之间的一个或多个非导电层，其可以帮助氮化镓材料的沉积。提供通孔，其从器件的背面延伸穿过非导电层，以使得沉积在通孔内的电触点与例如器件顶部的电触头之间能够导电。因此，本发明的装置可以是垂直导通的。在其他情况下，通孔可以没有电接触，例如，以增强光提取。示例性器件包括激光二极管（LD），发光二极管（LED），功率整流二极管，FET（例如HFET），耿氏效应二极管和变容二极管等。

2. 发明公开

EP2779227A2 Semiconductor package having multi-phase power inverter with internal temperature sensor 审中-公开
标题翻译： Halbleitergehäusemit mehrphasigem Wechselrichter mit internem Temperatursensor
公开(公告)号：EP2779227A2
公开(公告)日：2014-09-17
申请号：EP14156467.4
申请日：2014-02-25
申请人： International Rectifier Corporation
发明人： Fernando, Dean , Barbosa, Roel , Takahashi, Toshio
IPC分类号： H01L23/34
CPC分类号： H01L23/34 , H01L23/49562 , H01L23/49575 , H01L2224/05554 , H01L2224/0603 , H01L2224/45144 , H01L2224/45147 , H01L2224/48137 , H01L2224/4903 , H01L2224/49111 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/30111 , H01L2924/00 , H01L2924/00014
摘要： According to an exemplary implementation, a semiconductor package includes a multi-phase power inverter having power switches and situated on a leadframe of the semiconductor package. The semiconductor package further includes a temperature sensor situated on the leadframe, where the temperature sensor is configured to generate a sensed temperature of the power switches. The semiconductor package also includes a driver circuit configured to drive the power switches of the multi-phase power inverter responsive to the sensed temperature. The temperature sensor can be on a common IC with the driver circuit. Furthermore, the semiconductor package can include an over-temperature protection circuit configured to provide over-temperature protection to the multi-phase power inverter using the sensed temperature.
摘要翻译：根据示例性实施例，半导体封装包括具有电源开关并位于半导体封装的引线框架上的多相电力逆变器。半导体封装还包括位于引线框架上的温度传感器，其中温度传感器被配置为产生功率开关的感测温度。半导体封装还包括驱动器电路，其被配置为响应于所感测的温度来驱动多相功率逆变器的功率开关。温度传感器可以与驱动器电路在公共IC上。此外，半导体封装可以包括过温保护电路，其被配置为使用感测的温度向多相功率逆变器提供过温保护。

3. 发明公开

EP2775622A1 RF switch gate control 审中-公开
标题翻译： HF-Schaltergateansteuerung
公开(公告)号：EP2775622A1
公开(公告)日：2014-09-10
申请号：EP14157558.9
申请日：2014-03-04
申请人： International Rectifier Corporation
发明人： Briere, Michael A.
IPC分类号： H03K17/693 , H04B1/48 , H03K17/06
CPC分类号： H03K17/162 , H03K17/693 , H03K2017/066 , H03K2217/0054
摘要： In one implementation, a switching circuit 300 includes a pass switch 306a, 306b, including group III-V, for example III-Nitride, transistors coupled between an input 302a, 302b, of the switching circuit and an output 304 of the switching circuit. The switching circuit further includes a shunt switch 326a, 326b,configured to ground the input of the switching circuit while the pass switch is disabled. The switching circuit also includes a gate control transistor 310a, 310b, 340a, 340b configured to reduce resistance between a control terminal of the pass switch and/or the shunt switch and gate of the group III-V transistor of the pass switch and/or the shunt switch so as to enable and disable the pass switch and/or shunt switch. The gate control transistor can be coupled across a gate resistor 312a, 312b, 31c, 312d of the pass switch and/or the shunt switch. The gate control transistor can reduce the resistance in order to lower the OFF state impedance of the pass switch and/or the shunt switch.
摘要翻译：在一个实现中，开关电路300包括通过开关306a，306b，其包括III-V族，例如III-Nitride，耦合在开关电路的输入端302a，302b和开关电路的输出端304之间的晶体管。开关电路还包括分路开关326a，326b，其配置成在通路开关被禁用时将开关电路的输入接地。开关电路还包括栅极控制晶体管310a，310b，340a，340b，其被配置为降低通路开关的控制端和/或并联开关与通过开关的III-V晶体管的栅极之间的电阻和/或分流开关，以便启用和禁用通过开关和/或并联开关。栅极控制晶体管可以跨过通路开关和/或并联开关的栅极电阻器312a，312b，31c，312d耦合。栅极控制晶体管可以减小电阻以降低通路开关和/或并联开关的截止状态阻抗。

4. 发明公开

EP2775519A2 Power quad flat no-lead (PQFN) semiconductor package with leadframe islands for multi-phase power inverter 审中-公开
标题翻译：功率四平面无铅（PQFN） - 高精度电容器（LattungsrahmeninselnfürMehrphasen-Leistungswechselrichter）
公开(公告)号：EP2775519A2
公开(公告)日：2014-09-10
申请号：EP13199756.1
申请日：2013-12-30
申请人： International Rectifier Corporation
发明人： Fernando, Dean , Barbosa, Roel
IPC分类号： H01L23/495
CPC分类号： H01L23/49575 , H01L23/4952 , H01L23/49548 , H01L23/49582 , H01L2224/05554 , H01L2224/0603 , H01L2224/45144 , H01L2224/45147 , H01L2224/48137 , H01L2224/48247 , H01L2224/4903 , H01L2224/49111 , H01L2224/49505 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a U-phase output node situated on a first leadframe island of a leadframe, a V-phase output node situated on a second leadframe island of said leadframe, and a W-phase output node situated on a W-phase die pad of said leadframe. The first leadframe island can be on a first leadframe strip of the leadframe, where the first leadframe strip is connected to a U-phase die pad of the leadframe. The second leadframe island can be on a second leadframe strip of the leadframe, where the second leadframe strip is connected to a V-phase die pad of the leadframe. A first W-phase power switch is situated on the W-phase die pad. Furthermore, at least one wirebond is connected to the W-phase die pad and to a source of a second W-phase power switch. The W-phase die pad can be a W-phase output terminal of the PQFN package.
摘要翻译：根据示例性实现，功率四边形无引线（PQFN）封装包括位于引线框架的第一引线框岛上的U相输出节点，位于所述引线框架的第二引线框岛上的V相输出节点，以及位于所述引线框架的W相管芯焊盘上的W相输出节点。第一引线框岛可以在引线框架的第一引线框条上，其中第一引线框条连接到引线框架的U相管芯焊盘。第二引线框岛可以位于引线框架的第二引线框条上，其中第二引线框条连接到引线框架的V相管芯焊盘。第一W相电源开关位于W相芯片焊盘上。此外，至少一个引线键连接到W相管芯焊盘和第二W相电源开关的源极。 W相管芯焊盘可以是PQFN封装的W相输出端子。

5. 发明公开

EP2765597A2 System for sintering using a pressurized gas or liquid 审中-公开
标题翻译：系统，用于烧结用加压气体或液体的装置
公开(公告)号：EP2765597A2
公开(公告)日：2014-08-13
申请号：EP14153204.4
申请日：2014-01-30
申请人： International Rectifier Corporation
发明人： Hauenstein, Henning M.
IPC分类号： H01L21/60 , B22F3/15
CPC分类号： B32B37/10 , B22F3/15 , B22F2003/153 , H01L21/64 , H01L23/3735 , H01L23/5385 , H01L24/75 , H01L24/83 , H01L24/97 , H01L2224/291 , H01L2224/29294 , H01L2224/29339 , H01L2224/32145 , H01L2224/32227 , H01L2224/32245 , H01L2224/7511 , H01L2224/753 , H01L2224/75304 , H01L2224/75314 , H01L2224/7598 , H01L2224/83055 , H01L2224/83075 , H01L2224/83085 , H01L2224/83091 , H01L2224/83203 , H01L2224/83208 , H01L2224/83209 , H01L2224/8384 , H01L2224/97 , H01L2924/01322 , H01L2924/10253 , H01L2924/1033 , H01L2924/1203 , H01L2924/1304 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13064 , H01L2924/13091 , H01L2924/15747 , H01L2924/15787 , H01L2924/3512 , H01L2924/00014 , H01L2924/05432 , H01L2924/05032 , H01L2924/05042 , H01L2924/01002 , H01L2924/0101 , H01L2924/01018 , H01L2924/01036 , H01L2924/01054 , H01L2924/01086 , H01L2924/00 , H01L2924/00012 , H01L2224/83 , H01L2924/01007
摘要： In an exemplary implementation, a system for producing an electrical module includes a pressure chamber (210) configured to receive a first body (202), a second body (204), and a sinter material (206) therebetween. The system further includes a pressure generator (224) configured to apply non-mechanical pressure to a gas or a liquid (232) in the pressure chamber (210) in order to attach the first body (202) to the second body (204) using the sinter material (206). The pressure chamber (210) is configured to enclose the first body (202) over the second body (204). Furthermore, the pressure chamber (210) includes a bottom opening configured to receive at least the first body (202).
摘要翻译：有在，以示例性的执行之间，在电气模块生产的系统包括：被配置为接收第一主体（202），第二主体（204），和烧结的材料（206）的压力室（210）。该系统还包括被配置以便所述第一主体（202）连接到所述第二机体，将非机械压力的气体或在压力室（210）的液体（232）的压力发生器（224）（204）使用烧结材料（206）。压力室（210）被配置在所述第二主体（204）以封闭所述第一主体（202）。进一步，压力室（210）包括配置成接收至少所述第一主体（202）的底部开口。

6. 发明公开

EP2722884A1 Semiconductor package with conductive carrier integrated heat spreader 审中-公开
标题翻译： Halbleiterpackung mit leitendemträgerintegriertemWärmeverteiler
公开(公告)号：EP2722884A1
公开(公告)日：2014-04-23
申请号：EP13185620.5
申请日：2013-09-23
申请人： International Rectifier Corporation
发明人： Cho, Eung San , Sawle, Andrew N. , Pavier, Mark , Cutler, Daniel
IPC分类号： H01L25/07 , H01L25/11 , H01L23/00 , H01L23/495
CPC分类号： H01L21/84 , H01L21/4825 , H01L21/4871 , H01L21/561 , H01L23/3121 , H01L23/49562 , H01L23/49568 , H01L23/49575 , H01L24/16 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/072 , H01L25/117 , H01L25/16 , H01L25/18 , H01L25/50 , H01L2224/16245 , H01L2224/24137 , H01L2224/24245 , H01L2224/29101 , H01L2224/2929 , H01L2224/32245 , H01L2224/73259 , H01L2224/73267 , H01L2224/8382 , H01L2224/8384 , H01L2224/92224 , H01L2224/92244 , H01L2924/10253 , H01L2924/10323 , H01L2924/10325 , H01L2924/1033 , H01L2924/10334 , H01L2924/10341 , H01L2924/10344 , H01L2924/10346 , H01L2924/10355 , H01L2924/10356 , H01L2924/10357 , H01L2924/10358 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/1426 , H01L2924/1815 , H01L2924/00 , H01L2924/0665 , H01L2924/00014 , H01L2924/014
摘要： In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.
摘要翻译：在一个实施方案中，半导体封装包括具有管芯侧的控制导电载体和将半导体封装连接到安装表面的相反的输入/输出（I / O）侧。半导体封装还包括具有附接到控制导电载体的管芯侧的控制漏极的功率转换器开关级的控制FET。控制导电载体被配置为将由控制FET产生的热量吸收到安装表面中。半导体封装包括具有另一管芯侧的同步导电载体和将半导体封装连接到安装表面的另一个相反的I / O侧，以及功率转换器开关级的同步FET，其具有连接到同步的管芯侧的同步源导电载体。

7. 发明公开

EP2518766A3 Power module with press-fit clamps 审中-公开
标题翻译：电源模块带有压入式夹子
公开(公告)号：EP2518766A3
公开(公告)日：2014-03-19
申请号：EP12160152.0
申请日：2012-03-19
申请人： International Rectifier Corporation
发明人： Hauenstein, Henning M.
IPC分类号： H01L25/07 , H01L23/48 , H01L25/18
CPC分类号： H01L25/072 , H01L23/48 , H01L24/72 , H01L25/18 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01R12/721 , H01R12/778 , H05K1/117 , H05K2201/10386 , H01L2924/00
摘要： According to an exemplary embodiment, a bondwireless power module residing on a top surface of a substrate includes at least one input power pad providing power to the module and at least one output current pad providing output current from the module. At least one press-fit input power clamp engages a top side of the at least one input power pad, and engages a bottom surface of the substrate. Also, at least one press-fit output current clamp engages a top side of the at least one output current pad, and engages the bottom surface of the substrate. The at least one press-fit input power clamp can include at least one top prong and at least one bottom prong. Furthermore, the at least one bottom prong can press the input power pad into the at least one top prong.
摘要翻译：根据示例性实施例，驻留在基板的顶表面上的无接合线电力模块包括向模块提供电力的至少一个输入电力焊盘和提供来自模块的输出电流的至少一个输出电流焊盘。至少一个压配合输入电力夹具接合所述至少一个输入电源焊盘的顶侧，并接合所述衬底的底表面。而且，至少一个压配合输出电流钳接合至少一个输出电流焊盘的顶侧，并且接合衬底的底表面。该至少一个压配合输入动力夹具可以包括至少一个顶部叉脚和至少一个底部叉脚。此外，所述至少一个底部插脚可将输入电源衬垫压入至少一个顶部插脚中。

8. 发明公开

EP2690657A2 Robust fuse-protected transistor 审中-公开
标题翻译： Robuster，durch Sicherunggeschützter晶体管
公开(公告)号：EP2690657A2
公开(公告)日：2014-01-29
申请号：EP13176249.4
申请日：2013-07-12
申请人： International Rectifier Corporation
发明人： Briere, Michael A.
IPC分类号： H01L23/525 , H01L23/62 , H01L29/423 , H01L29/417
CPC分类号： H01L29/778 , H01L23/4824 , H01L23/5256 , H01L23/62 , H01L29/2003 , H01L29/41758 , H01L29/42316 , H01L29/4238 , H01L2924/0002 , H01L2924/00
摘要： According to an exemplary implementation, a transistor includes a plurality of drain fingers interdigitated with a plurality of source fingers. The transistor further includes a gate configured to control current conduction between the plurality of drain fingers and the plurality of source fingers. Additionally, the transistor includes a plurality of drain fuses, each being configured to electrically disconnect a drain finger of the plurality of drain fingers from remaining ones of the plurality of drain fingers. At least one of the plurality of drain fuses can electrically couple the drain finger to a common drain pad. The transistor may further include a plurality of source fuses, each being configured to electrically disconnect a source finger of the plurality of source fingers from remaining ones of the plurality of source fingers.
摘要翻译：根据示例性实施方式，晶体管包括与多个源极指相交叉的多个漏极指状物。晶体管还包括配置成控制多个漏极指与多个源极之间的电流导通的栅极。另外，晶体管包括多个漏极保险丝，每个漏极保险丝被配置为将多个排水指的排出手指与多个排水指中剩余的排水手指电断开。多个漏极熔丝中的至少一个可以将漏极手指电耦合到公共漏极焊盘。晶体管可以进一步包括多个源保险丝，每个源保险丝被配置为将多个源极指的源极手指与多个源极指状物中的剩余源极电气断开。

9. 发明公开

EP2363880A3 Monolithic integration of silicon and group III-V devices 审中-公开
标题翻译：硅和III-V器件单片集成
公开(公告)号：EP2363880A3
公开(公告)日：2014-01-22
申请号：EP11001112.9
申请日：2011-02-11
申请人： International Rectifier Corporation
发明人： Briere, Michael A.
IPC分类号： H01L21/8258 , H01L27/06 , H03K17/567 , H03K17/74
CPC分类号： H01L27/0629 , H01L21/8258 , H01L27/0688 , H01L29/2003 , H01L29/7786 , H03K17/567 , H03K17/74
摘要： Disclosed is a monolithically integrated silicon and group III-V device that includes a group III-V transistor (228) formed in a III-V semiconductor body disposed over a silicon substrate. At least one via extends through the III-V semiconductor body to couple at least one terminal of the group III-V transistor to a silicon device formed in the silicon substrate. The silicon device can be a Schottky diode (226), and the group III-V transistor can be a GaN HEMT. In one embodiment an anode of the Schottky diode is formed in the silicon substrate. In another embodiment, the anode of the Schottky diode is formed in a lightly doped epitaxial silicon layer (204) atop the silicon substrate. In one embodiment a parallel combination of the Schottky diode and the group III-V transistor is formed, while in another embodiment is series combination is formed.

10. 发明公开

EP2639832A2 Group III-V and group IV composite diode 审中-公开
标题翻译： Gruppe-III-IV和Gruppe-IV-Verbunddiode
公开(公告)号：EP2639832A2
公开(公告)日：2013-09-18
申请号：EP13157960.9
申请日：2013-03-06
申请人： International Rectifier Corporation
发明人： Briere, Michael A. , McDonald, Tim
IPC分类号： H01L25/18 , H01L25/07
CPC分类号： H01L25/07 , H01L25/18 , H01L2224/16 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/30107 , H01L2924/00
摘要： In one implementation, a group III-V and group IV composite diode includes a group IV diode in a lower active die, the group IV diode having an anode situated on a bottom side of the lower active die. The group III-V and group IV composite diode also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a cathode of the group IV diode using a through-semiconductor via (TSV) of the upper active die.
摘要翻译：在一个实施方式中，III-V族和IV族复合二极管包括下部有源管芯中的IV族二极管，该IV族二极管具有位于下部有源管芯底部的阳极。 III-V族和IV族复合二极管还包括堆叠在下部有源管芯上方的上部有源管芯中的III-V族晶体管，具有漏极，源极和位于顶部的栅极的III-V族晶体管上活动模具的一侧。 III-V族晶体管的源极使用上部有源裸片的贯通半导体通孔（TSV）与组IV二极管的阴极电耦合。

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