会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明公开
    • CHIP SCALE PACKAGE LIGHT EMITTING DIODE
    • EP4297105A3
    • 2024-04-24
    • EP23208095.2
    • 2018-12-10
    • Seoul Viosys Co., Ltd.
    • KIM, Jong KyuKANG, Min WooOH, Se HeeLIM, Hyoung Jin
    • H01L33/48H01L33/62H01L33/10H01L33/42H01L33/38H01L33/40
    • H01L33/10H01L33/42H01L33/62H01L33/382H01L33/486H01L33/405H01L33/385H01L33/387
    • A light emitting diode module, comprising a printed circuit board (1023), and a light emitting diode (1021) disposed on the substrate, the light emitting diode including a substrate (21), a first conductivity type semiconductor layer (23), a mesa (M) disposed on the first conductivity type semiconductor layer (23), and including an active layer (25) and a second conductivity type semiconductor layer (27), an ohmic contact layer (28) disposed on the mesa (M) and electrically connected to the second conductivity type semiconductor layer (27), a lower insulation layer (33) covering the mesa (M), and including at least one first opening (33a1) exposing the first conductivity type semiconductor layer (23) and a second opening (33a2), a first pad metal layer (35a) disposed on the lower insulation layer (33), and electrically connected to the first conductivity type semiconductor layer (23) through the at least one first opening (33a1), a second pad metal layer (35b) disposed on the lower insulation layer (33), and electrically connected to the ohmic contact layer (28) through the second opening (33a2), a upper insulation layer (37) covering the first and second pad metal layers (35a, 35b) and including first opening (37a) exposing the first pad metal layer (35a) and a second opening (37b) exposing the second pad metal layer (35b), a first bump pad (39a) disposed on the upper insulation (37), and electrically connected to the first pad metal layer (35a) through the first opening (37a) of the upper insulation layer(37), and a second bump pad (39b) disposed on the upper insulation (37), and electrically connected to the second pad metal layer (35b) through the second opening (37b) of the upper insulation layer(37), wherein the first pad metal layer (35a) includes a protrusion having an outer contact portion (35a1) that contacts the first conductivity type semiconductor layer (23) near the edge of the substrate (21), and wherein the first pad metal layer (35a) includes a region that has a wide width and a region that has a narrow width extending from thereof.
    • 5. 发明公开
    • SEMICONDUCTOR LIGHT-EMITTING ELEMENT
    • EP4270497A2
    • 2023-11-01
    • EP23169662.6
    • 2023-04-25
    • Nichia Corporation
    • HOSOKAWA, YasunobuOTSUKA, Takumi
    • H01L33/38H01L33/64H01L33/32H01L33/24
    • A semiconductor light-emitting element includes a semiconductor structure including an n-side semiconductor layer including a first region, a second region located on an outer periphery of the first region, and a plurality of third regions surrounded by the first region in a plan view, a light-emitting layer disposed on the first region, and a p-side semiconductor layer disposed on the light-emitting layer; a first insulating film disposed on the semiconductor structure and defining a plurality of first openings, each located above a corresponding one of the plurality of third regions and a plurality of second openings located above the p-side semiconductor layer; an n-side electrode disposed on the first insulating film and electrically connected to the n-side semiconductor layer through the plurality of first openings; at least one n-pad electrode disposed in the second region and electrically connected to the n-side electrode; a second insulating film disposed on the first insulating film and defining a plurality of third openings, each located at a position overlapping a corresponding one of the plurality of second openings; and a p-pad electrode disposed on the second insulating film and electrically connected to the p-side semiconductor layer through the plurality of third openings. The p-pad electrode covers the first region and the plurality of third regions in a plan view. Two or more of the plurality of first openings are located around a corresponding one of the plurality of third openings in a plan view.