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1. 发明授权

EP2176886B1 CASCODE CURRENT SENSOR FOR DISCRETE POWER SEMICONDUCTOR DEVICES 有权
标题翻译： KASKODENSTROMSENSORFÜRDISKRETE HALBLEITERBAUELEMENTE
公开(公告)号：EP2176886B1
公开(公告)日：2016-04-20
申请号：EP08794842.8
申请日：2008-07-29
申请人： Advanced Analogic Technologies, Inc.
发明人： WILLIAMS, Richard, K.
IPC分类号： H01L27/088 , H01L23/00 , G01R1/20 , G01R19/00 , H01L29/78 , H03K17/082 , H01L23/495 , H01L29/423 , H01L29/10 , H01L29/417 , H02M1/00
CPC分类号： G01R19/0092 , G01R1/203 , H01L23/49575 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/17 , H01L24/25 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L27/088 , H01L29/1087 , H01L29/41758 , H01L29/4238 , H01L29/7833 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05558 , H01L2224/05599 , H01L2224/0603 , H01L2224/13099 , H01L2224/16145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/48464 , H01L2224/48599 , H01L2224/49111 , H01L2224/49171 , H01L2224/73207 , H01L2224/73257 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/10253 , H01L2924/12032 , H01L2924/12035 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13063 , H01L2924/13091 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H02M2001/0009 , H03K17/0822 , H03K17/18 , H03K2217/0027 , H01L2924/00 , H01L2924/00012
摘要： A cascode current sensor includes a main MOSFET and a sense MOSFET. The drain terminal of the main MOSFET is connected to a power device whose current is to be monitored, and the source and gate terminals of the main MOSFET are connected to the source and gate terminals, respectively, of the sense MOSFET. The drain voltages of the main and sense MOSFETs are equalized, in one embodiment by using a variable current source and negative feedback. The gate width of the main MOSFET is typically larger than the gate width of the sense MOSFET. Using the size ratio of the gate widths, the current in the main MOSFET is measured by sensing the magnitude of the current in the sense MOSFET. Inserting the relatively large MOSFET in the power circuit minimizes power loss.
摘要翻译：共源共栅电流传感器包括主MOSFET和感测MOSFET。主MOSFET的漏极端子连接到要监控电流的功率器件，并且主MOSFET的源极和栅极端子分别连接到感测MOSFET的源极和栅极端子。在一个实施例中，通过使用可变电流源和负反馈来使主感测MOSFET和感测MOSFET的漏极电压相等。主MOSFET的栅极宽度通常大于读出MOSFET的栅极宽度。使用栅极宽度的尺寸比，通过感测MOSFET中电流的大小来测量主MOSFET中的电流。在电源电路中插入相对较大的MOSFET可以最大限度地降低功耗。

2. 发明公开

EP2624302A1 Trench power MOSFET 审中-公开
标题翻译：沟槽Leistungs-MOSFET
公开(公告)号：EP2624302A1
公开(公告)日：2013-08-07
申请号：EP13154655.8
申请日：2004-03-04
申请人： Advanced Analogic Technologies, Inc. , Advanced Analogic Technologies (Hong Kong) Limited
发明人： Williams, Richard K. , Cornell, Michael E. , Chan, Wai Tien
IPC分类号： H01L29/78 , H01L21/336 , H01L29/423 , H01L29/49
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/456 , H01L29/4925 , H01L29/4933 , H01L29/4941 , H01L29/66734 , H01L29/7811
摘要： Power MOSFET's and fabrication processes for power MOSFET's use a continuous conductive gate structure within trenches to avoid device topology problems caused when a gate bus extends above a substrate. The conductive gate structure forms trench gates in an active device region and forms a gate bus in a gate bus trench. The gate bus trench connects to device trenches and can be wide to facilitate forming a contact to the gate bus. The device trenches can be narrow to maximize device density. The gate bus and/or gates contain a metal/silicide to reduce resistance, and polysilicon surrounds the metal/silicide to prevent metal atoms from penetrating the gate oxide layers. A CMP process can planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with forming self-aligned or conventional contacts in the active device region.
摘要翻译：功率MOSFET和功率MOSFET的制造工艺在沟槽内使用连续的导电栅极结构，以避免栅极总线延伸到衬底上方引起的器件拓扑问题。导电栅极结构在有源器件区域中形成沟槽栅极，并在栅极总线沟槽中形成栅极总线。栅极总线沟槽连接到器件沟槽，并且可以宽以便于形成与栅极总线的接触。器件沟槽可以窄到最大化器件密度。栅极总线和/或栅极包含金属/硅化物以降低电阻，并且多晶硅围绕金属/硅化物以防止金属原子穿过栅极氧化物层。 CMP工艺可以平坦化导电栅极结构和/或覆盖绝缘层。该过程与在有源器件区域中形成自对准或常规触点相容。

3. 发明授权

EP1488307B1 SINGLE WIRE SERIAL INTERFACE 有权
标题翻译：串行单线接口
公开(公告)号：EP1488307B1
公开(公告)日：2011-04-20
申请号：EP03745656.3
申请日：2003-03-26
申请人： Advanced Analogic Technologies, Inc.
发明人： D'ANGELO, Kevin , BROWN, David, Alan , SUNG, John, K. , NILSSON, Jan , WILLIAMS, Richard, K.
IPC分类号： G06F1/32
CPC分类号： G06F1/28 , G06F1/04 , G06F1/06 , G06F1/12 , G06F1/22 , G06F9/4403 , G06F13/4291 , G09G3/3406 , G09G5/10 , G09G2320/0233 , H05B33/0803 , H05B33/0815 , H05B33/0851
摘要： A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin.

4. 发明授权

EP1543546B8 PROCESS FOR FABRICATING AN ISOLATED FIELD EFFECT TRANSISTOR IN AN EPI-LESS SUBSTRATE 有权
标题翻译：用于在无EPI的衬底中制造隔离的场效应晶体管的工艺
公开(公告)号：EP1543546B8
公开(公告)日：2010-06-16
申请号：EP03788439.2
申请日：2003-08-13
申请人： Advanced Analogic Technologies, Inc.
发明人： WILLIAMS, Richard, K. , CORNELL, Michael, E. , CHAN, Wai Tien
IPC分类号： H01L21/30 , H01L21/46 , H01L21/3205 , H01L21/332 , H01L21/336 , H01L21/425 , H01L29/72 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L21/26513 , H01L21/743 , H01L21/761 , H01L21/823878 , H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L29/0878 , H01L29/1083 , H01L29/42368 , H01L29/66136 , H01L29/6625 , H01L29/735 , H01L29/7816 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： A process of fabricating a semiconductor device is disclosed comprising providing a semiconductor substrate of a first conductivity type, the substrate not containing an epitaxial layer; forming a first mask on a surface of the substrate, said first mask having a first opening defining a location of a first deep layer in a lateral dimension; implanting a dopant of a second conductivity type through the first opening to form the first deep layer; forming a second mask on the surface of the substrate, said second mask having a second opening defining a location of a second deep layer in the lateral dimension, a width of the second opening being less that a width of the first opening; and implanting dopant of the first conductivity type through the second opening to form the second deep layer. The projected range of the implant of dopant of the first conductivity type is less than the projected range of the implant of dopant of the second conductivity type such that the second deep layer overlaps and extends above the first deep layer. Alternatively, the projected range of the implant of dopant of the first conductivity type is greater than the projected range of the implant of dopant of the second conductivity type such that the second deep layer overlaps and extends below the first deep layer.

5. 发明授权

EP1543546B1 PROCESS FOR FABRICATING AN ISOLATED FIELD EFFECT TRANSISTOR IN AN EPI-LESS SUBSTRATE 有权
标题翻译：方法生产分离的场效应晶体管IN A EPI地段衬底
公开(公告)号：EP1543546B1
公开(公告)日：2010-03-31
申请号：EP03788439.2
申请日：2003-08-13
申请人： Advanced Analogic Technologies, Inc.
发明人： WILLIAMS, Richard, K. , CORNELL, Michael, E. , CHAN, Wai Tien
IPC分类号： H01L21/30 , H01L21/46 , H01L21/3205 , H01L21/332 , H01L21/336 , H01L21/425 , H01L29/72 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L21/26513 , H01L21/743 , H01L21/761 , H01L21/823878 , H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L29/0878 , H01L29/1083 , H01L29/42368 , H01L29/66136 , H01L29/6625 , H01L29/735 , H01L29/7816 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： A process of fabricating a semiconductor device is disclosed comprising providing a semiconductor substrate of a first conductivity type, the substrate not containing an epitaxial layer; forming a first mask on a surface of the substrate, said first mask having a first opening defining a location of a first deep layer in a lateral dimension; implanting a dopant of a second conductivity type through the first opening to form the first deep layer; forming a second mask on the surface of the substrate, said second mask having a second opening defining a location of a second deep layer in the lateral dimension, a width of the second opening being less that a width of the first opening; and implanting dopant of the first conductivity type through the second opening to form the second deep layer. The projected range of the implant of dopant of the first conductivity type is less than the projected range of the implant of dopant of the second conductivity type such that the second deep layer overlaps and extends above the first deep layer. Alternatively, the projected range of the implant of dopant of the first conductivity type is greater than the projected range of the implant of dopant of the second conductivity type such that the second deep layer overlaps and extends below the first deep layer.

6. 发明公开

EP2082244A2 CURRENT LIMIT DETECTOR 有权
标题翻译： STROMBEGRENZUNGSDETEKTOR
公开(公告)号：EP2082244A2
公开(公告)日：2009-07-29
申请号：EP07844244.9
申请日：2007-10-12
申请人： Advanced Analogic Technologies, Inc.
发明人： SO, John Sung Ko
IPC分类号： G01R27/08
CPC分类号： H02H9/025 , H02H3/006
摘要： Devices, such as mobile devices, may be exposed to short circuit and output overload events. To protect against such events, mobile devices typically include current limit circuits. Some current limit circuits may involve user programmable function. User programmable function may need accurate current limit detectors. One approach to improving resolution and accuracy of current limit detectors using a single resistive device is to magnify the operating current range. Various embodiments of the present invention include devices and methods for detecting pre-programmed current limits.

7. 发明公开

EP1958249A1 ISOLATION STRUCTURES FOR SEMICONDUCTOR INTEGRATED CIRCUIT SUBSTRATES AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：隔离结构用于在集成电路和方法半导体衬底用于形成
公开(公告)号：EP1958249A1
公开(公告)日：2008-08-20
申请号：EP06844906.5
申请日：2006-12-07
申请人： Advanced Analogic Technologies Inc.
发明人： WILLIAMS, Richard, K.
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76232
摘要： Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.

8. 发明公开

EP2771876A1 LOW COST LED DRIVER WITH IMPROVED SERIAL BUS 审中-公开
标题翻译：具有改进的串行总线低成本的LED驱动器
公开(公告)号：EP2771876A1
公开(公告)日：2014-09-03
申请号：EP12842902.4
申请日：2012-10-23
申请人： Advanced Analogic Technologies, Inc.
发明人： WILLIAMS, Richard K. , D'ANGELO, Kevin , BROWN, David A.
IPC分类号： G09G3/14 , H04N5/52 , G06F19/00
CPC分类号： H04N5/57 , H05B33/083 , H05B33/0842 , H05B37/0254
摘要： An LED driver IC for driving exiernal strings of LEDs comprises a prefix register and a data register connected in series with each other and with the prefix and data registers in other driver ICs. The prefix and data registers of the driver ICs are connected in a daisy chain arrangement with an interface IC. The interface IC loads data identifying a functional latch into the prefix register and data defsnrag a functional condition into tlie data register of each driver IC. The data in the data register is then transferred to the functional latch to control the functional condition within the LED driver IC,

9. 发明授权

EP1573822B1 COMPLEMENTARY BIPOLAR TRANSISTORS WITH TRENCH-CONSTRAINED SINKERS AND ISOLATION REGIONS 有权
标题翻译：互补双极抓斗LIMITED下沉区和隔离区域
公开(公告)号：EP1573822B1
公开(公告)日：2012-03-14
申请号：EP03788490.5
申请日：2003-08-13
申请人： Advanced Analogic Technologies, Inc.
发明人： WILLIAMS, Richard, K. , CORNELL, Michael, E. , CHAN, Wai Tien
IPC分类号： H01L21/331 , H01L21/8228 , H01L21/8224 , H01L27/082
CPC分类号： H01L27/0826 , H01L21/8224 , H01L21/82285 , H01L27/0821 , H01L29/6625 , H01L29/66272 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa. When the substrate is subjected to thermal processing, the buried layer diffuses upward, the dopant in the mesa diffuses downward until the two dopants merge to form an isolation region or a sinker extending downward from the surface of the epitaxial layer to the buried layer. In another embodiment, dopant is implanted between dielectrically filled trenches at a high energy up to several MeV, then diffused, combining the benefits of deep implantation and trenched constrained diffusion to achive deep diffusions with a minimal thermal budget.

10. 发明公开

EP2290695A1 Trench-constrained isolation diffusion in a semiconductor material 审中-公开
标题翻译： Grabenbegrenzte扩散zur隔离在einem Halbleitermaterial
公开(公告)号：EP2290695A1
公开(公告)日：2011-03-02
申请号：EP10189464.0
申请日：2003-08-13
申请人： Advanced Analogic Technologies, Inc.
发明人： Williams, Richard K. , Cornell, Michael , Chan, Wai Tien
IPC分类号： H01L29/00 , H01L27/095
CPC分类号： H01L27/0826 , H01L21/8224 , H01L21/82285 , H01L27/0821 , H01L29/6625 , H01L29/66272 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate includes a pair of trenches (408A,408B) filled with a dielectric material (406). Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped regions diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer (410) is formed at an interface between an epitaxial layer (402) and a substrate (400), at a location generally below the dopant in the mesa.; When the substrate is subjected to thermal processing, the buried layer diffuses upward, the dopant in the mesa diffuses downward until the two dopants merge to form an isolation region or a sinker extending downward from the surface of the epitaxial layer to the buried layer. In another embodiment, dopant is implanted between dielectrically filled trenches at a high energy up to several MeV, then diffused, combining the benefits of deep implantation and trenched constrained diffusion to achieve deep diffusions with a minimal thermal budget.
摘要翻译：半导体衬底包括填充有电介质材料（406）的一对沟槽（408A，408B）。引入到沟槽之间的台面的掺杂剂被限制为当衬底经受热处理时横向扩散。因此，半导体器件可以在衬底上更紧密地间隔开，并且可以增加器件的封装密度。另外，沟槽约束掺杂区域比无约束扩散更快和更深地扩散，从而减少完成所需深度扩散所需的时间和温度。该技术可以用于诸如双极晶体管的半导体器件以及将器件彼此电隔离的隔离区域。在一组实施例中，在外延层（402）和衬底（400）之间的界面处，在台面的通常低于掺杂剂的位置处形成掩埋层（410）。当衬底经受热处理时，掩埋层向上扩散，台面中的掺杂剂向下扩散直到两个掺杂剂合并形成从外延层的表面向埋入层向下延伸的隔离区域或沉降片。在另一个实施例中，掺杂剂以高达几MeV的高能量注入电介质填充的沟槽之间，然后扩散，结合深度注入和沟槽约束扩散的优点，以最小的热预算实现深度扩散。

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