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    • 5. 发明公开
    • Semiconductor memory device
    • Halbleiterspeichervorrichtung
    • EP1560221A2
    • 2005-08-03
    • EP05250434.7
    • 2005-01-27
    • Sharp Kabushiki Kaisha
    • Inoue, KojiMorikawa, YoshinaoShimaoka, AtsushiTamai, Yukio
    • G11C7/06G11C7/12
    • G11C7/062G11C7/06G11C7/12G11C7/14G11C8/08
    • A semiconductor memory device comprises a column readout voltage supply circuit which supplies a predetermined first voltage when readout is selected and supplies a predetermined second voltage which is different from the fist voltage when the readout is not selected, to each column selection line, a row readout voltage supply circuit which supplies the second voltage to each row selection line at the time of readout, a sense circuit which detects a current flowing in the selected row selection line separately from a current flowing in the non-selected row selection lines to detect an electric resistance state of the selected memory cell at the time of readout, and a column voltage displacement prevention circuit which prevents displacement of a supplied voltage level for each of the non-selected column selection lines at the time of readout.
    • 半导体存储器件包括列读出电压供给电路,当选择读出时提供预定的第一电压,并且当未选择读出时将提供与第一电压不同的预定第二电压提供给每列选择线,行读出 电压供给电路,其在读出时向每行选择线提供第二电压;感测电路,其检测与在未选择的行选择线中流动的电流分开地在所选择的行选择线中流动的电流,以检测电 在读出时所选择的存储单元的电阻状态和列电压位移防止电路,用于在读出时防止每个未选择的列选择线提供的电压电平的位移。
    • 6. 发明公开
    • Nonvolatile semiconductor memory device, and programming method and erasing method thereof
    • NichtflüchtigerSpeicher und sein Programmier- undLöschverfahren
    • EP1489620A2
    • 2004-12-22
    • EP04253628.4
    • 2004-06-17
    • SHARP KABUSHIKI KAISHA
    • Tamai, YukioInoue, KohjiMorita, Teruaki
    • G11C11/15G11C16/28
    • G11C13/0007G11C13/0069G11C16/3427G11C2013/009G11C2213/31G11C2213/77
    • One end of each variable resistive element (22), which forms a memory array (1), in the same row is connected to the same word line (20) and the other end of each variable resistive element (22) in the same column is connected to the same bit line (21). A first word line voltage is selected and applied to the selected word line, a second word line voltage is selected and applied to the unselected word lines, a first bit line voltage is selected and applied to the selected bit line, and a second bit line voltage is selected and applied to the unselected bit lines. The voltage difference between the first word line voltage and the first bit line voltage is set at a value that is no less than the first voltage difference that changes the resistance value of a variable resistive element, and the voltage difference between the first word line voltage and the second bit line voltage, the voltage difference between the second word line voltage and the first bit line voltage and the voltage difference between the second word line voltage and the second bit line voltage are respectively set at a value that is no greater than the second voltage difference that does not change the resistance value of a variable resistive element.
    • 在同一行中形成存储器阵列(1)的每个可变电阻元件(22)的一端连接到相同的字线(20),而每个可变电阻元件(22)的另一端连接在同一列 连接到相同的位线(21)。 选择第一字线电压并将其施加到所选字线,选择第二字线电压并将其施加到未选字线,选择第一位线电压并将其施加到所选择的位线,并且将第二位线电压 电压被选择并施加到未选择的位线。 将第一字线电压和第一位线电压之间的电压差设定为不小于改变可变电阻元件的电阻值的第一电压差和第一字线电压之间的电压差 和第二位线电压,第二字线电压与第一位线电压之间的电压差和第二字线电压与第二位线电压之间的电压差分别设定为不大于 不改变可变电阻元件的电阻值的第二电压差。
    • 8. 发明公开
    • Writing method of variable resistance memory device
    • Schreibverfahrenfüreinen Speicher mitveränderlichemWiderstand
    • EP1612805A1
    • 2006-01-04
    • EP05254028.3
    • 2005-06-28
    • SHARP KABUSHIKI KAISHA
    • Hosoi, YasunariTamai, YukioIshihara, KazuyaKobayashi, ShinjiAwaya, Nobuyoshi
    • G11C13/00
    • G11C29/50G11C13/0007G11C13/0069G11C29/50008G11C2013/009G11C2213/31
    • A variable resistance element is configured to be provided with a perovskite-type oxide (2) between a first electrode (1) and a second electrode (3), of which electric resistance between the first electrode (1) and the second electrode (3) is changed by applying a voltage pulse of a predetermined polarity between the first electrode (1) and the second electrode (3), and the variable resistance element has a resistance hysteresis characteristic, in which a changing rate of a resistance value is changed from positive to negative with respect to increase of a cumulative pulse applying time in the application of the voltage pulse. The voltage pulse is applied to the variable resistance element so that the cumulative pulse applying time is not longer than a specific cumulative pulse applying time, in which the changing rate of the resistance value is changed from positive to negative with respect to increase of the cumulative pulse applying time in the resistance hysteresis characteristic.
    • 可变电阻元件被配置为在第一电极(1)和第二电极(3)之间设置有钙钛矿型氧化物(2),其中第一电极(1)和第二电极(3)之间的电阻 )通过在第一电极(1)和第二电极(3)之间施加预定极性的电压脉冲而改变,并且可变电阻元件具有电阻滞后特性,其中电阻值的变化率从 相对于施加电压脉冲的累积脉冲施加时间的增加而言,为正。 电压脉冲被施加到可变电阻元件,使得累积脉冲施加时间不长于特定的累积脉冲施加时间,其中电阻值的变化率相对于累积的增加而从正变化到负 脉冲施加时间在电阻滞后特性。