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    • 4. 发明公开
      EP1677348A1 Method for manufacturing non-volatile memory cells and periphery transistors 有权 转让
    • Method for manufacturing non-volatile memory cells and periphery transistors
    • 斯德哥尔摩和西伯利亚革兰氏代谢产物（Verfahren zur Herstellung vonnichtflüchtigenSpeicherzellen und Peripherietransistoren
    • EP1677348A1
    • 2006-07-05
    • EP05028380.3
    • 2005-12-23
    • STMicroelectronics S.r.l.
    • Pavan, Alessia , Servalli, Giorgio , Clementi, Gesare
    • H01L21/8247
    • H01L27/11526 , H01L27/105 , H01L27/11539
    • Method for manufacturing non volatile memory devices integrated on a semiconductor substrate (1) and comprising a matrix (2) of memory cells and an associated circuitry (3), the method comprising the following steps:

      forming a plurality of gate electrodes (2a) of the memory cells projecting from the semiconductor substrate (1) in the matrix (2), the plurality of gate electrodes (2a) comprising a plurality of conductive layers (5, 7) and at least one conductive layer (7') in said circuitry (3);
      forming conductive regions (9, 10) of the memory cells in the semiconductor substrate (1),
      forming a filling dielectric layer (13) on the whole semiconductor substrate (1) until the plurality of gate electrodes (2a) of the cells and of the conductive layer (7') formed in the circuitry (3) are completely covered,
      removing said conform filling dielectric layer (13) until upper portions (2b) of the plurality of gate electrodes (2a) of the cells are exposed and the conductive layer (7') formed in the circuitry (3) is completely exposed,
      defining a plurality of gate electrodes (3a) of the transistors of the circuitry (3) in the conductive layer (7') formed in the circuitry (3),
      forming source and drain regions of the transistors of the circuitry (3) in the semiconductor substrate (1).

      The method also comprises the following steps:

      forming spacers on the side walls of said plurality of gate electrodes (3a) of the transistors of said circuitry (3):
      forming a silicide layer (17) on said plurality of electrodes (2a) of the memory cells, on said plurality of gate electrodes (3a) of the transistors of said circuitry (3) and on said conductive regions of the transistors of said circuitry (3);
      forming a layer (18) of filling material on the whole of said semiconductor substrate (1) until said plurality of gate electrodes (3a) of the transistors of said circuitry (3) is completely covered and said plurality of matrix electrodes (2a) is completely covered;
      defining contacts (19) for the conductive regions of said matrix (2) and of said circuitry (3) formed in a same step or in different steps.
    • 一种用于制造集成在半导体衬底（1）上并包括存储器单元的矩阵（2）和相关电路（3）的非易失性存储器件的方法，所述方法包括以下步骤：形成多个栅电极 所述存储单元从所述矩阵（2）中的所述半导体衬底（1）突出，所述多个栅电极（2a）包括多个导电层（5,7）和所述电路中的至少一个导电层（7'） （3）; 在所述半导体衬底（1）中形成所述存储单元的导电区域（9,10），在所述半导体衬底（1）的整个半导体衬底（1）上形成填充介电层（13），直到所述单元的多个栅电极（2a） 形成在电路（3）中的导电层（7'）被完全覆盖，去除所述顺应填充介电层（13），直到电池的多个栅电极（2a）的上部（2b）被暴露并且导电 形成在电路（3）中的层（7'）完全暴露，限定电路（3）中形成在电路（3）中的导电层（7'）中的电路（3）的晶体管的多个栅电极（3a） 形成半导体衬底（1）中的电路（3）的晶体管的源极和漏极区域。 该方法还包括以下步骤：在所述电路（3）的晶体管的所述多个栅电极（3a）的侧壁上形成间隔物：在所述电路的所述多个电极（2a）上形成硅化物层（17） 在所述电路（3）的晶体管的所述多个栅电极（3a）上和所述电路（3）的晶体管的所述导电区上的存储单元; 在整个所述半导体衬底（1）上形成填充材料层（18），直到所述电路（3）的晶体管的多个栅电极（3a）被完全覆盖，并且所述多个矩阵电极（2a）是 完全覆盖 为相同步骤或不同步骤形成的所述矩阵（2）和所述电路（3）的导电区域定义触点（19）。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明公开
      EP1816675A1 Manufacturing process of spacers for high-voltage transistors in an EEPROM device 审中-公开
    • Manufacturing process of spacers for high-voltage transistors in an EEPROM device
    • 在einer EEPROM-Vorrichtung的Herstellungsverfahren von SpacernfürHochspannungstransistoren
    • EP1816675A1
    • 2007-08-08
    • EP06425059.0
    • 2006-02-03
    • STMicroelectronics S.r.l.
    • Costantini, Sonia , Pavan, Alessia , Servalli, Giorgio
    • H01L21/8247 , H01L27/105
    • H01L27/11526 , H01L27/105 , H01L27/11534 , H01L27/11539 , H01L27/11543 , H01L27/11546
    • Process for manufacturing a non volatile memory electronic device (2) integrated on a semiconductor substrate (1) which comprises a matrix of non volatile memory cells (4), said memory cells (4) organised in rows, called word lines, and columns, called bit lines and an associated circuitry comprising high voltage transistors (3), comprising the steps of:
      - forming, by means of a photo-lithographic process which provides the use of a first photo-lithographic mask, gate electrodes (12) of the high voltage transistors (3) projecting from a first portion (A) of the semiconductor substrate (1).
      - forming first spacers (15) on the side walls of the gate electrodes (12) of said high voltage transistors (3) of a first length (L1),
      - forming, by means of a photo-lithographic process which provides the use of a second photo lithographic mask which covers said high voltage transistors (3), gate electrodes (16) of said memory cells (4) projecting from a second portion (B) of said semiconductor substrate (1), each of said gate electrodes (16) of memory cells (4) comprising a floating gate electrode (FG) and a control gate electrode (CG)
    • 一种集成在半导体衬底（1）上的非易失性存储器件（2）的制造方法，该半导体衬底（1）包括非易失性存储器单元（4）的矩阵，所述存储单元（4）被组织成行，称为字线和列， 所谓的位线和包括高压晶体管（3）的相关电路，包括以下步骤： - 通过提供使用第一光刻掩模的光刻工艺，形成所述第一光刻掩模的栅电极（12） 从半导体衬底（1）的第一部分（A）伸出的高电压晶体管（3）。 - 在第一长度（L1）的所述高压晶体管（3）的栅极（12）的侧壁上形成第一间隔物（15）， - 通过光刻工艺形成，所述光刻工艺提供使用 覆盖所述高压晶体管（3）的第二光刻掩模，从所述半导体衬底（1）的第二部分（B）突出的所述存储单元（4）的栅电极（16），每个所述栅电极 ）包括浮栅电极（FG）和控制栅电极（CG）的存储单元（4）
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明公开
      EP1804293A1 Process for manufacturing a non volatile memory electronic device 审中-公开
    • Process for manufacturing a non volatile memory electronic device
    • Herstellungsverfahrenfürein elektronisches Festwertspeicherbauelement
    • EP1804293A1
    • 2007-07-04
    • EP05425942.9
    • 2005-12-30
    • STMicroelectronics S.r.l.
    • Brazzelli, Daniela , Servalli, Giorgio , Carollo, Enzo
    • H01L27/115 , H01L21/8247 , H01L21/768
    • H01L21/7682 , H01L21/764 , H01L21/76897 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11534 , H01L2924/3011
    • Process for manufacturing a non volatile electronic device integrated on a semiconductor substrate (2) which comprises a plurality of non volatile memory cells (1) being organised in matrix and an associated circuitry, comprising the steps of:
      - forming gate electrodes (7) of the memory cells (1) projecting from the semiconductor substrate (2), each of the gate electrodes (7) comprising a first dielectric layer (3), a floating gate electrode (4), a second dielectric layer (5) and a control gate electrode (6) coupled to a respective word line, at least one first portion of the gate electrodes (7) of the memory cells (1) being separated from each other by first openings (15) of a first width (D),
      - forming source and drain regions (8) of the memory cells (1) in the semiconductor substrate (2), the source and drain regions (8) of the memory cells (1) being aligned with the gate electrodes (7) of the memory cells (1),
      - forming gate electrodes of transistors of the circuitry projecting from the semiconductor substrate (2), each of the gate electrodes of the circuitry comprising a first dielectric layer of the circuitry and a first conductive layer of the circuitry,
      - forming source and drain regions of the transistors in the semiconductor substrate (2), the source and drain regions of the transistors being aligned with the gate electrodes (7) of the transistors, the process being characterised in that it comprises the following steps:

      - depositing, on the whole device, a third non conform dielectric layer (10) so as to completely fill in the first openings (15) and to form air-gaps (16) between the gate electrodes belonging to the first portion of the gate electrodes (7) of the memory cells (1).
    • 一种用于制造集成在半导体衬底（2）上的非易失性电子器件的方法，该半导体衬底包括以矩阵形式组织的多个非易失性存储器单元（1）和相关联的电路，包括以下步骤： - 形成栅电极 从半导体衬底（2）突出的存储单元（1），每个栅电极（7）包括第一介电层（3），浮栅电极（4），第二介电层（5）和控制 栅极电极（6），其耦合到相应的字线，存储单元（1）的栅电极（7）的至少一个第一部分通过第一宽度（D）的第一开口（15）彼此分开， - 在所述半导体衬底（2）中形成所述存储单元（1）的源区和漏区（8），所述存储单元（1）的源区和漏区（8）与所述半导体衬底 存储单元（1）， - 形成所述电路的晶体管的栅电极 在所述半导体衬底（2）中，所述电路的每个栅电极包括所述电路的第一介电层和所述电路的第一导电层， - 形成所述半导体衬底（2）中的所述晶体管的源区和漏区， 晶体管的源极和漏极区域与晶体管的栅电极（7）对准，该工艺的特征在于其包括以下步骤： - 在整个器件上沉积第三非标准电介质层（10） 以便完全填充第一开口（15）并且在属于存储单元（1）的栅电极（7）的第一部分的栅电极之间形成气隙（16）。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明公开
      EP1804289A2 Non volatile memory electronic device integrated on a semiconductor substrate 有权 转让
    • Non volatile memory electronic device integrated on a semiconductor substrate
    • 在ein Halbleitersubstrat integrierte elektronische Vorrichtung mitnichtflüchtigemSpeicher
    • EP1804289A2
    • 2007-07-04
    • EP06026787.9
    • 2006-12-22
    • STMicroelectronics S.r.l.
    • Servalli, Giorgio , Capetti, Gianfranco , Cantú, Pietro
    • H01L21/8247 , H01L27/115
    • H01L27/115 , H01L27/11519 , H01L27/11521
    • A non volatile memory device is described being integrated on semiconductor substrate (11, 110) and comprising a matrix of non volatile memory cells (12, 120) organised in rows, called word lines, and columns, called bit lines, the device comprising:
      - a plurality of active areas (13, 130) formed on the semiconductor substrate (11, 110) comprising a first and a second group (G1, G2; G3, G4) of active areas,
      - the non volatile memory cells (12, 120) being integrated in the first group (G1, G3) of active areas, each non volatile memory cell (12, 120) comprising a source region, a drain region and a floating gate electrode coupled to a control gate electrode, at least one group (14, 140) of the memory cells (12, 120) sharing a common source region (15, 150) integrated on the semiconductor substrate (11, 110), the device being characterised in that:

      - said plurality of active areas (13, 130) are equidistant from each other,
      - a contact region (16, 160) is integrated in the second group (G2, G4) of active areas (13, 130) and is provided with at least one common source contact (17, 170) of said common source region (15, 150).
    • 描述了非易失性存储器件集成在半导体衬底（11,110）上，并且包括被称为位线的称为字线的行的非易失性存储器单元（12,120）的矩阵，所述器件包括： - 形成在半导体衬底（11,110）上的多个有源区（13,130），包括有源区的第一和第二组（G1，G2; G3，G4）， - 非易失性存储单元（12， 120）集成在有源区的第一组（G1，G3）中，每个非易失性存储单元（12,120）包括耦合到控制栅极的源极区，漏极区和浮栅，至少一个 所述存储单元（12,120）的组（14,140）共享共同的半导体衬底（11,110）上的公共源极区域（15,150），所述器件的特征在于： - 所述多个有源区域 13,130）彼此等距， - 接触区域（16,160）被集成在第二组（G2 ，G4）的有源区域（13,130），并且设置有所述公共源极区域（15,150）的至少一个公共源极触点（17,170）。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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