专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP0126424B1 Process for making polycide structures 失效
标题翻译：制备聚合物结构的方法
公开(公告)号：EP0126424B1
公开(公告)日：1990-11-28
申请号：EP84105540.3
申请日：1984-05-16
申请人： International Business Machines Corporation
发明人： Roberts, Stanley , White, Francis Roger
IPC分类号： H01L21/28 , H01L21/31
CPC分类号： H01L29/66575 , H01L21/0272 , H01L21/28061 , H01L21/28123 , H01L21/32134 , H01L21/32137 , H01L21/7688 , H01L21/76889 , Y10S148/084 , Y10S438/951

2. 发明授权

EP0531723B1 Three-dimensional multichip packaging method 失效
标题翻译：三维多芯片封装的生产方法
公开(公告)号：EP0531723B1
公开(公告)日：1997-03-12
申请号：EP92113573.7
申请日：1992-08-10
申请人： International Business Machines Corporation
发明人： Bertin, Claude Louis , Farrar, Paul Alden, Sr. , Kalter, Howard Leo , Kelley, Gordon Arthur, Jr. , van der Hoeven, Willem Bernard , White, Francis Roger
IPC分类号： H01L25/065
CPC分类号： H01L25/0657 , H01L25/0652 , H01L2224/05009 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555

3. 发明公开

EP0531723A1 Three-dimensional multichip packaging method 失效
标题翻译： Dreidimensionale Mehrchippackungen und Herstellungsverfahren。
公开(公告)号：EP0531723A1
公开(公告)日：1993-03-17
申请号：EP92113573.7
申请日：1992-08-10
申请人： International Business Machines Corporation
发明人： Bertin, Claude Louis , Farrar, Paul Alden, Sr. , Kalter, Howard Leo , Kelley, Gordon Arthur, Jr. , van der Hoeven, Willem Bernard , White, Francis Roger
IPC分类号： H01L25/065
CPC分类号： H01L25/0657 , H01L25/0652 , H01L2224/05009 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555
摘要： A fabrication method and resultant three-dimensional multichip package having a densely stacked array of semiconductor chips interconnected at least partially by means of a plurality of metallized trenches are disclosed. The fabrication method includes providing an integrated circuit chip (50) having high aspect ratio metallized trenches (62) therein extending from a first surface to a second surface (58) thereof. An etch stop layer is provided proximate the termination position of the metallized trenches with the semiconductor substrate (52). Next the integrated circuit device is affixed to a carrier (70) such that the surface of the supporting substrate is exposed and substrate is thinned from the integrated circuit device until exposing at least some of the plurality of metallized trenches therein. Electrical contact can thus be made to the active layer of the integrated circuit chip via the exposed metallized trenches (66). Specific details of the fabrication method and the resultant multichip package are set forth.
摘要翻译：公开了一种具有通过多个金属化沟槽至少部分互连的半导体芯片的密集堆叠阵列的制造方法和所得的三维多芯片封装。制造方法包括提供在其中从其第一表面延伸到第二表面（58）的具有高纵横比的金属化沟槽（62）的集成电路芯片（50）。在金属化沟槽的与半导体衬底（52）的终止位置附近提供蚀刻停止层。接下来，集成电路器件被固定到载体（70）上，使得支撑衬底的表面被暴露，并且衬底从集成电路器件变薄，直到暴露其中的多个金属化沟槽中的至少一些。因此，可以通过暴露的金属化沟槽（66）将集成电路芯片的有源层进行电接触。阐述制造方法和所得多芯片封装的具体细节。

4. 发明公开

EP0158715A3 Process for making semiconductor devices using high temperature treatment in an oxidizing environment 失效
标题翻译：在氧化环境中使用高温处理制造半导体器件的工艺
公开(公告)号：EP0158715A3
公开(公告)日：1986-07-16
申请号：EP84114427
申请日：1984-11-30
申请人： International Business Machines Corporation
发明人： Geipel, Henry John Jr. , Schaefer, Charles Andrew , White, Francis Roger , Wursthorn, John Michael
IPC分类号： H01L21/316 , H01L21/322
CPC分类号： H01L21/324 , H01L21/3145 , H01L21/32105 , Y10S438/911
摘要： A process is provided for fabricating a semiconductor structure wherein the structure has to be exposed to certain oxidizing conditions during certain of its processing steps, such as its high temperature annealing in an oxidizing ambient. It includes depositing a "sacrificial" layer, such as silicon, to provide a uniformly oxidizing surface during subsequent annealing operations. This sacrificial layer, which oxidizes uniformly, produces an oxide layer which also etches uniformly. Thus, after the annealing is completed, the surface oxide is removed through etching and the remaining sacrificial layer is then also removed through a different etching step.

5. 发明授权

EP0178440B1 Process of making dual well CMOS semiconductor structure 失效
标题翻译：制造双芯CMOS半导体结构的工艺
公开(公告)号：EP0178440B1
公开(公告)日：1991-11-27
申请号：EP85111088.2
申请日：1985-09-03
申请人： International Business Machines Corporation
发明人： Kinney, Wayne Irving , Koburger, Charles William , Lasky, Jerome Brett , Nesbit, Larry Alan , White, Francis Roger , Troutman, Ronald Roy
IPC分类号： H01L21/82 , H01L21/76 , H01L27/092 , H01L29/06 , H01L21/00
CPC分类号： H01L21/76218 , H01L21/033 , H01L21/823892 , H01L27/0928 , H01L29/0638 , Y10S148/043 , Y10S148/053 , Y10S148/10 , Y10S148/157

6. 发明公开

EP0178440A3 Process of making dual well CMOS semiconductor structure 失效
标题翻译：制造双芯CMOS半导体结构的工艺
公开(公告)号：EP0178440A3
公开(公告)日：1988-01-27
申请号：EP85111088
申请日：1985-09-03
申请人： International Business Machines Corporation
发明人： Kinney, Wayne Irving , Koburger, Charles William , Lasky, Jerome Brett , Nesbit, Larry Alan , White, Francis Roger , Troutman, Ronald Roy
IPC分类号： H01L21/82 , H01L21/76 , H01L27/08 , H01L29/06 , H01L21/00
CPC分类号： H01L21/76218 , H01L21/033 , H01L21/823892 , H01L27/0928 , H01L29/0638 , Y10S148/043 , Y10S148/053 , Y10S148/10 , Y10S148/157
摘要： A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells (26, 28) to each other and also of the field isolation doping regions (32, 10) to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks (30) for subsequent formation of the field-doping regions (32, 10); and a dopant-transmitter during the ion-implanation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers (32, 10) self-aligned to the wells (26, 28) so that, with a subsequent masking step, oxide field isolations (36, 38) are defined over the doped oxide layers (32, 10). A heat cyde is then used to drive the field dopants into the corresponding field-doping regions (40, 42).

7. 发明公开

EP0158715A2 Process for making semiconductor devices using high temperature treatment in an oxidizing environment 失效
标题翻译：一种用于通过在氧化气氛中高温处理手段的生产半导体器件的过程。
公开(公告)号：EP0158715A2
公开(公告)日：1985-10-23
申请号：EP84114427.2
申请日：1984-11-30
申请人： International Business Machines Corporation
发明人： Geipel, Henry John Jr. , Schaefer, Charles Andrew , White, Francis Roger , Wursthorn, John Michael
IPC分类号： H01L21/316 , H01L21/322
CPC分类号： H01L21/324 , H01L21/3145 , H01L21/32105 , Y10S438/911
摘要： A process is provided for fabricating a semiconductor structure wherein the structure has to be exposed to certain oxidizing conditions during certain of its processing steps, such as its high temperature annealing in an oxidizing ambient. It includes depositing a "sacrificial" layer, such as silicon, to provide a uniformly oxidizing surface during subsequent annealing operations. This sacrificial layer, which oxidizes uniformly, produces an oxide layer which also etches uniformly. Thus, after the annealing is completed, the surface oxide is removed through etching and the remaining sacrificial layer is then also removed through a different etching step.

8. 发明授权

EP0158715B1 Process for making semiconductor devices using high temperature treatment in an oxidizing environment 失效
标题翻译：在氧化环境中使用高温处理制造半导体器件的工艺
公开(公告)号：EP0158715B1
公开(公告)日：1990-01-24
申请号：EP84114427.2
申请日：1984-11-30
申请人： International Business Machines Corporation
发明人： Geipel, Henry John Jr. , Schaefer, Charles Andrew , White, Francis Roger , Wursthorn, John Michael
IPC分类号： H01L21/316 , H01L21/322
CPC分类号： H01L21/324 , H01L21/3145 , H01L21/32105 , Y10S438/911

9. 发明公开

EP0126424A3 Process for making polycide structures 失效
标题翻译：制备聚合物结构的方法
公开(公告)号：EP0126424A3
公开(公告)日：1988-01-13
申请号：EP84105540
申请日：1984-05-16
申请人： International Business Machines Corporation
发明人： Roberts, Stanley , White, Francis Roger
IPC分类号： H01L21/28 , H01L21/31
CPC分类号： H01L29/66575 , H01L21/0272 , H01L21/28061 , H01L21/28123 , H01L21/32134 , H01L21/32137 , H01L21/7688 , H01L21/76889 , Y10S148/084 , Y10S438/951
摘要： @ On an insulating layer (12) a polysilicon layer (14) and a silicide layer (22) are deposited and by a lift-off technique a dry etching mask (28) is formed of a metal being not eroded during the dry etching and being removable by wet etching with etchants that do not etch the underlying material, and at least the areas of the polysilicon layer (14) not covered by dry etching mask (28) are removed by dry etching. The silicide layer (22) may be deposited either through a chemical vapor deposition process or through the co-deposition of a silicide forming metal and silicon followed by a low temperature annealing step prior to dry etching. To avoid in said latter case a diffusion of the metal mask into the underlying material during this low temperature annealing, the process provides for the formation of a diffusion barrier layer (22) between the dry etching metal mask (28) and the underlying material. The polycide structures are used for electrode and wiring interconnection applications.

10. 发明公开

EP0178440A2 Process of making dual well CMOS semiconductor structure 失效
标题翻译：一种用于制造双阱CMOS半导体结构的方法。
公开(公告)号：EP0178440A2
公开(公告)日：1986-04-23
申请号：EP85111088.2
申请日：1985-09-03
申请人： International Business Machines Corporation
发明人： Kinney, Wayne Irving , Koburger, Charles William , Lasky, Jerome Brett , Nesbit, Larry Alan , White, Francis Roger , Troutman, Ronald Roy
IPC分类号： H01L21/82 , H01L21/76 , H01L27/092 , H01L29/06 , H01L21/00
CPC分类号： H01L21/76218 , H01L21/033 , H01L21/823892 , H01L27/0928 , H01L29/0638 , Y10S148/043 , Y10S148/053 , Y10S148/10 , Y10S148/157
摘要： A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells (26, 28) to each other and also of the field isolation doping regions (32, 10) to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks (30) for subsequent formation of the field-doping regions (32, 10); and a dopant-transmitter during the ion-implanation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers (32, 10) self-aligned to the wells (26, 28) so that, with a subsequent masking step, oxide field isolations (36, 38) are defined over the doped oxide layers (32, 10). A heat cyde is then used to drive the field dopants into the corresponding field-doping regions (40, 42).

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式