专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP0736896A2 Process for making low-leakage contacts 失效
标题翻译： Herstellungsverfahren von Kontakten mit niedrigem Leckstrom
公开(公告)号：EP0736896A2
公开(公告)日：1996-10-09
申请号：EP96480030.4
申请日：1996-03-05
申请人： International Business Machines Corporation
发明人： Givens, John Howard , Koburger III, Charles William , Lasky, Jerome Brett
IPC分类号： H01L21/285
CPC分类号： H01L23/485 , H01L21/76843 , H01L21/76897 , H01L2924/0002 , H01L2924/00
摘要： A method of making a semiconductor device having low-leakage borderless contacts by etching contact openings over first and second electronic elements of opposite dopant type, conformally depositing a thin doped polysilicon layer, protecting the electronic element of similar dopant-type and removing the thin doped polysilicon layer over the oppositely doped electronic element and then depositing tungsten within the contact openings.
摘要翻译：通过在相对掺杂剂类型的第一和第二电子元件上蚀刻接触开口制造具有低泄漏无边界接触的半导体器件的方法，保形地沉积薄掺杂多晶硅层，保护类似掺杂剂型的电子元件并去除薄掺杂多晶硅层在相对掺杂的电子元件上方，然后在接触开口内沉积钨。

2. 发明公开

EP0543158A3 Method of conducting strap formation in a semiconductor device 失效
标题翻译：在半导体器件中导带形成的方法
公开(公告)号：EP0543158A3
公开(公告)日：1993-12-29
申请号：EP92117856.2
申请日：1992-10-19
申请人： International Business Machines Corporation
发明人： Lam, Chung Hon , Lasky, Jerome Brett , Hill, Craig Marshall , Nakos, James Spiros , Holmes, Steven John , Geissler, Stephen Frank , Lord, David Kennedy
IPC分类号： H01L21/90
CPC分类号： H01L21/32134 , H01L21/768
摘要： The invention provides a method for electrically connecting a polysilicon-filled trench (12) to a diffusion region (10) in a semiconductor device, wherein the trench (12) and diffusion region (10) are separated by a dielectric (14). The method provides for formation of a strap or bridge contact by utilizing a diffusion barrier layer (18) which prevents diffusion into an overlying polysilicon layer (32) when a subsequent boron (16) out-diffusion step is performed. Selective etching is then utilized to remove the polysilicon layer (32) where no boron has diffused, leaving a polysilicon strap connecting the trench and diffusion region.

3. 发明公开

EP0303061A2 Process for forming a planarized, metal-strapped polysilicon gate FET 失效
标题翻译： Prozess zur Ausbildung eines planarisierten，mit MetallüberzogenenPolysilizium-Gatter-FET。
公开(公告)号：EP0303061A2
公开(公告)日：1989-02-15
申请号：EP88111163.7
申请日：1988-07-12
申请人： International Business Machines Corporation
发明人： Abernathey, John Robert , Cronin, John Edward , Lasky, Jerome Brett
IPC分类号： H01L21/28 , H01L21/90
CPC分类号： H01L29/66575 , H01L21/2257 , H01L21/28061 , H01L29/41783 , H01L29/66545
摘要： A process for forming a planarized, low sheet resistance FET. A gate stack is defined on an exposed surface of a semiconductor substrate, the gate stack including a gate mask disposed on a patterned polysilicon layer. First and second diffusion having first and second silicide electrodes are then formed on the substrate, to provide low sheet resistance source and drain electrodes. An insulating layer is then formed on the substrate, and is planarized to expose an upper surface of the gate mask. The gate mask is then removed in wet H₃PO₄ to define an aperture in the insulating layer that exposes the polysilicon layer, and a conductive material is selectively grown on the substrate to provide a metal-strapped polysilicon gate electrode that is relatively co-planar with the planarized insulating layer.
摘要翻译：用于形成平坦化的低片电阻FET的工艺。栅极堆叠被限定在半导体衬底的暴露表面上，栅极堆叠包括设置在图案化多晶硅层上的栅极掩模。然后在基板上形成具有第一和第二硅化物电极的第一和第二扩散，以提供低的薄层电阻源极和漏极。然后在衬底上形成绝缘层，并将其平坦化以露出栅极掩模的上表面。然后在湿H 3 PO 4中除去栅极掩模以限定暴露多晶硅层的绝缘层中的孔，并且在衬底上选择性地生长导电材料，以提供金属带状多晶硅栅电极，其与平坦化绝缘层。

4. 发明公开

EP0166218A3 Silicon-on-insulator transistors 失效
标题翻译：绝缘体绝缘体晶体管
公开(公告)号：EP0166218A3
公开(公告)日：1987-09-02
申请号：EP85106383
申请日：1985-05-24
申请人： International Business Machines Corporation
发明人： Abernathey, John Robert , Kinney, Wayne Irving , Lasky, Jerome Brett , Stiffler, Scott Richard
IPC分类号： H01L21/20 , H01L21/76 , H01L27/06
CPC分类号： H01L27/0688 , H01L21/2007 , H01L21/76251 , H01L21/8221 , Y10S148/135 , Y10S148/15 , Y10S148/164
摘要： A shared element semiconductor structure in which the insulating layer of a silicon-on-insulator structure is patterned to form a gate oxide (40). The bulk semiconductor (24) underlying the insulating layer (40) is defined into an FET (field-effect transistor) with its gate region below the gate oxide. The epitaxial layer above the insulating layer (40) is defined into another FET with its drain region (60) above the gate oxide (40), whereby the drain region (60) also operates as the gate electrode for the bulk FET. Also described is a method of forming a silicon on insulator substrate with insulating layer usable as a gate oxide by means of bonding a silicon substrate to an oxidized epitaxial layer on another silicon seed substrate and then removing the seed substrate.

5. 发明公开

EP0624899A2 Oxidation of silicon nitride in semiconductor devices 失效
标题翻译： Herstellung von Halbleitenden Anordnungen中的氧化铀 - 硝酸盐。
公开(公告)号：EP0624899A2
公开(公告)日：1994-11-17
申请号：EP94104574.2
申请日：1994-03-23
申请人： International Business Machines Corporation
发明人： Geissler, Stephen Frank , Korejwa, Josef Warren , Lasky, Jerome Brett , Pai, Pai-Hung
IPC分类号： H01L21/314 , H01L21/28
CPC分类号： H01L21/3144
摘要： A silicon nitride layer in a semiconductor device is oxidized by exposure to a mixture of an oxygen reactant and a dilute amount of a fluorine-containing compound at a temperature sufficiently high to substantially cause the oxidation of the silicon nitride. Generally, a temperature greater than about 600°C is sufficient to cause such oxidation, although some oxidation may occur at lower temperatures. The concentration of the fluorine-containing compound is also not critical, but is generally between about 100 to 1500 ppm by volume relative to the total mixture volume. Preferably, NF₃ is the fluorine-containing compound, and a temperature greater than about 700°C at a concentration of between about 100 to 1000 ppm is used.
摘要翻译：通过在足够高的温度下暴露于氧反应物和稀释的含氟化合物的混合物来氧化半导体器件中的氮化硅层，从而基本上使氮化硅氧化。通常，大于约600℃的温度足以引起这种氧化，尽管在较低温度下可能发生一些氧化。含氟化合物的浓度也不是关键的，但相对于总混合物体积通常为约100至1500ppm体积。优选地，NF 3是含氟化合物，并且使用浓度在约100至1000ppm之间的大于约700℃的温度。

6. 发明公开

EP0531707A2 Semiconductor memory cell and memory array with inversion layer 失效
标题翻译： Halbleiterspeicherzelle und Speicherfeld mit einer Inversionsschicht。
公开(公告)号：EP0531707A2
公开(公告)日：1993-03-17
申请号：EP92113264.3
申请日：1992-08-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kauffmann, Bruce Alan , Lam, Chung Hon , Lasky, Jerome Brett
IPC分类号： H01L27/115 , G11C16/02
CPC分类号： H01L27/115
摘要： A memory cell (10, 50), suitable for electrically erasable programmable read only memories (EEPROMs), which has direct write cell capability is disclosed. The memory cell (10, 50) is fabricated on a substrate (12, 52) and uses an inversion source gate (18, 54) disposed above the substrate (12, 52) to generate a depletion source (IS) therein. The depletion source (IS) defines a channel region in the substrate (12, 52) with an associated drain (14, ID). An electrically isolated floating gate (26, 62) is disposed above the substrate (12, 52) so as to overlap at least a portion of the substrate channel region. Further, a program gate (30, 66) is disposed to overlap a portion of the floating gate (26, 62) and an access gate (34, 70) is also provided aligned at least partially over the substrate channel region such that a dual gate device is defined. An array of such memory cells (10, 50) is also disclosed.
摘要翻译：公开了一种适用于具有直接写入单元能力的电可擦除可编程只读存储器（EEPROM）的存储单元（10,50）。存储单元（10,50）被制造在衬底（12,52）上，并且使用设置在衬底（12,52）上方的反相源栅极（18,54）在其中产生耗尽源（IS）。耗尽源（IS）在衬底（12,52）中限定具有相关联的漏极（14，ID）的沟道区域。电隔离的浮动栅极（26,62）设置在衬底（12,52）上方，以便与衬底沟道区域的至少一部分重叠。此外，程序门（30,66）设置成与浮置栅极（26,62）的一部分重叠，并且还提供对准至少部分地在衬底沟道区域上方的存取栅极（34,70），使得双重定义门设备。还公开了这种存储器单元（10,50）的阵列。

7. 发明授权

EP0178440B1 Process of making dual well CMOS semiconductor structure 有权
标题翻译：制造双芯CMOS半导体结构的工艺
公开(公告)号：EP0178440B1
公开(公告)日：1991-11-27
申请号：EP85111088.2
申请日：1985-09-03
申请人： International Business Machines Corporation
发明人： Kinney, Wayne Irving , Koburger, Charles William , Lasky, Jerome Brett , Nesbit, Larry Alan , White, Francis Roger , Troutman, Ronald Roy
IPC分类号： H01L21/82 , H01L21/76 , H01L27/092 , H01L29/06 , H01L21/00
CPC分类号： H01L21/76218 , H01L21/033 , H01L21/823892 , H01L27/0928 , H01L29/0638 , Y10S148/043 , Y10S148/053 , Y10S148/10 , Y10S148/157

8. 发明公开

EP0178440A3 Process of making dual well CMOS semiconductor structure 有权
标题翻译：制造双芯CMOS半导体结构的工艺
公开(公告)号：EP0178440A3
公开(公告)日：1988-01-27
申请号：EP85111088
申请日：1985-09-03
申请人： International Business Machines Corporation
发明人： Kinney, Wayne Irving , Koburger, Charles William , Lasky, Jerome Brett , Nesbit, Larry Alan , White, Francis Roger , Troutman, Ronald Roy
IPC分类号： H01L21/82 , H01L21/76 , H01L27/08 , H01L29/06 , H01L21/00
CPC分类号： H01L21/76218 , H01L21/033 , H01L21/823892 , H01L27/0928 , H01L29/0638 , Y10S148/043 , Y10S148/053 , Y10S148/10 , Y10S148/157
摘要： A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells (26, 28) to each other and also of the field isolation doping regions (32, 10) to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks (30) for subsequent formation of the field-doping regions (32, 10); and a dopant-transmitter during the ion-implanation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers (32, 10) self-aligned to the wells (26, 28) so that, with a subsequent masking step, oxide field isolations (36, 38) are defined over the doped oxide layers (32, 10). A heat cyde is then used to drive the field dopants into the corresponding field-doping regions (40, 42).

9. 发明授权

EP0069327B1 Method of laser annealing a subsurface region in a semiconductor 失效
标题翻译：激光退火在半导体中的表面区域的方法
公开(公告)号：EP0069327B1
公开(公告)日：1987-09-09
申请号：EP82105775.9
申请日：1982-06-29
申请人： International Business Machines Corporation
发明人： Hansen, Howard Helge , Lasky, Jerome Brett , Silverman, Ronald R.
IPC分类号： H01L21/268 , H01L21/74
CPC分类号： H01L21/74 , H01L21/268 , Y10S148/092 , Y10S148/093

10. 发明授权

EP0284840B1 Method for forming uniform layers of material 失效
标题翻译：一种用于生产材料的均匀层中的处理。
公开(公告)号：EP0284840B1
公开(公告)日：1993-11-18
申请号：EP88103610.7
申请日：1988-03-08
申请人： International Business Machines Corporation
发明人： Lasky, Jerome Brett
IPC分类号： H01L21/304
CPC分类号： H01L21/764 , H01L21/304 , H01L21/31053 , H01L21/76264 , H01L21/76275 , H01L21/76289 , Y10S438/959 , Y10S438/97

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式