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51. 发明公开

EP2822038A1 INSULATED GATE BIPOLAR TRANSISTOR 有权
标题翻译：绝缘栅双极型晶体管
公开(公告)号：EP2822038A1
公开(公告)日：2015-01-07
申请号：EP13794783.4
申请日：2013-08-07
申请人： Huawei Technologies Co., Ltd.
发明人： ZHU, Yisheng , ZHANG, Jinping
IPC分类号： H01L29/739
CPC分类号： H01L29/404 , H01L29/0619 , H01L29/0638 , H01L29/0661 , H01L29/7397
摘要： Embodiments of the present invention provide an IGBT, which relates to the field of integrated circuit manufacturing, and may improve a problem of tail current when the IGBT is turned off. The IGBT includes a cell region on a front surface, a terminal region surrounding the cell region, an IGBT drift region of a first conductivity type, and an IGBT collector region on a back surface. The IGBT collector region is connected to the IGBT drift region and under the IGBT drift region. The IGBT drift region includes a first drift region under the cell region and a second drift region under the terminal region. The IGBT collector region includes a cell collector region of a heavily doped second conductivity type under the first drift region and a non-conductive isolation region adjacent to the cell collector region. A length of the non-conductive isolation region is smaller than or equal to a length of the terminal region, and a thickness of the non-conductive isolation region is larger than or equal to a thickness of the cell collector region.Turn-off loss of the IGBT may be reduced, and turn-off reliability may be improved.
摘要翻译：本发明实施例提供一种与集成电路制造领域相关的IGBT，可以改善IGBT关断时的尾电流问题。 IGBT包括在前表面上的单元区域，围绕单元区域的端子区域，第一导电类型的IGBT漂移区域和在后表面上的IGBT集电极区域。 IGBT集电极区域连接到IGBT漂移区域和IGBT漂移区域下方。 IGBT漂移区包括单元区下方的第一漂移区和端子区下方的第二漂移区。 IGBT集电极区域包括在第一漂移区域下方的重掺杂第二导电类型的单元集电极区域和与单元集电极区域相邻的非导电隔离区域。非导电隔离区的长度小于或等于端子区的长度，并且非导电隔离区的厚度大于或等于电池集电极区的厚度。切断损耗可以减小IGBT，并且可以改善关断可靠性。

52. 发明公开

EP2782122A3 Manufacturing method of JFET semiconductor device and JFET semiconductor device 有权转让
标题翻译：一种制造半导体JFET装置及半导体装置JFET的方法
公开(公告)号：EP2782122A3
公开(公告)日：2014-12-24
申请号：EP14160755.6
申请日：2014-03-19
申请人： Renesas Electronics Corporation
发明人： Kagotoshi, Yasuaki , Arai, Koichi , Yokoyama, Natsuki , Shimizu, Haruka
IPC分类号： H01L21/337 , H01L29/808
CPC分类号： H01L29/0619 , H01L29/1066 , H01L29/1608 , H01L29/42316 , H01L29/66068 , H01L29/66893 , H01L29/8083
摘要： A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n + -type source layer on a surface of an n - -type drift layer formed on an n + -type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n - -type drift layer with a silicon oxide film formed on the n - -type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n - -type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n - -type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

53. 发明公开

EP2784805A1 METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：EP2784805A1
公开(公告)日：2014-10-01
申请号：EP12851007.0
申请日：2012-10-02
申请人： Sumitomo Electric Industries, Ltd. , National University Corporation Nara Institute of Science and Technology
发明人： MASUDA, Takeyoshi , HATAYAMA, Tomoaki
IPC分类号： H01L21/336 , H01L21/205 , H01L21/302 , H01L21/3065 , H01L21/329 , H01L29/06 , H01L29/12 , H01L29/739 , H01L29/78 , H01L29/861 , H01L29/868
CPC分类号： H01L29/8613 , H01L21/02529 , H01L21/02576 , H01L21/0262 , H01L21/0475 , H01L21/3065 , H01L21/3083 , H01L29/045 , H01L29/06 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0661 , H01L29/12 , H01L29/1608 , H01L29/4236 , H01L29/4238 , H01L29/66068 , H01L29/739 , H01L29/78 , H01L29/7813 , H01L29/861 , H01L29/868 , Y10S438/931
摘要： On a substrate (1), a silicon carbide layer (19) provided with a main surface is formed. A mask (17) is formed to cover a portion of the main surface of the silicon carbide layer (19). The main surface of the silicon carbide layer (19) on which the mask (17) is formed is thermally etched using chlorine-based gas so as to provide the silicon carbide layer (19) with a side surface (SS) inclined relative to the main surface. The step of thermally etching is performed in an atmosphere in which the chlorine-based gas has a partial pressure of 50% or smaller.
摘要翻译：在衬底（1）上，形成具有主表面的碳化硅层（19）。掩模（17）形成为覆盖碳化硅层（19）的主表面的一部分。使用氯基气体对其上形成有掩模（17）的碳化硅层（19）的主表面进行热蚀刻，以便为碳化硅层（19）提供相对于所述碳化硅层（19）倾斜的侧表面主表面。热蚀刻工序在氯系气体的分压为50％以下的气氛下进行。

54. 发明公开

EP2630663A4 IMPROVED SCHOTTKY RECTIFIER 有权
标题翻译：改进肖特基整流器
公开(公告)号：EP2630663A4
公开(公告)日：2014-10-01
申请号：EP11835119
申请日：2011-10-20
申请人： VISHAY GEN SEMICONDUCTOR LLC
发明人： HSU CHIH-WEI , UDREA FLORIN , LIN YIH-YIN
IPC分类号： H01L29/872 , H01L21/329 , H01L29/868
CPC分类号： H01L29/66143 , H01L21/22 , H01L21/265 , H01L29/0619 , H01L29/872 , H01L29/8725

55. 发明公开

EP2580782A4 SCHOTTKY BARRIER DIODE WITH PERIMETER CAPACITANCE WELL JUNCTION 有权转让
标题翻译：与周长容量公路过渡肖特基二极管
公开(公告)号：EP2580782A4
公开(公告)日：2014-10-01
申请号：EP11810114
申请日：2011-06-29
申请人： IBM
发明人： ANDERSON FREDERICK G , LARY JENIFER E , RASSEL ROBERT M , STIDHAM MARK E
IPC分类号： H01L29/872 , H01L29/06 , H01L29/47
CPC分类号： H01L29/872 , H01L21/761 , H01L29/0619 , H01L29/0646 , H01L29/0692 , H01L29/66143

56. 发明公开

EP2782140A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：EP2782140A1
公开(公告)日：2014-09-24
申请号：EP14156325.4
申请日：2014-02-24
申请人： Kabushiki Kaisha Toshiba
发明人： Ota, Chiharu , Shimizu, Tatsuo , Nishio, Johji , Shinohe, Takashi
IPC分类号： H01L29/872 , H01L21/329 , H01L29/161 , H01L29/167
CPC分类号： H01L29/1608 , H01L29/0619 , H01L29/167 , H01L29/45 , H01L29/47 , H01L29/6606 , H01L29/872
摘要： A semiconductor device includes an n-type SiC substrate, an n-type SiC layer formed on the SiC substrate; a p-type first SiC region formed in the surface of the SiC layer and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D being a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the concentration of the element A in the combination(s) being higher than 0.33 but lower than 0.995, the concentration of the element A forming part of the combination(s) being not lower than 1 × 10 17 cm -3 and not higher than 1 × 10 22 cm -3 , a first electrode, and a second electrode.
摘要翻译：一种半导体器件包括：n型SiC衬底，形成在SiC衬底上的n型SiC层; 在SiC层的表面形成的含有p型杂质和n型杂质的p型第一SiC区域，p型杂质为元素A，n型杂质为元素D，元素A和元素D是Al，Ga或In和N的组合，和/或B和P的组合，组合中元素D的浓度与元素A的浓度之比（s ）高于0.33但低于0.995，形成所述组合的一部分的元素A的浓度不低于1×1017cm-3且不高于1×1022cm-3，第一电极和第二电极。

57. 发明公开

EP2782122A2 Manufacturing method of JFET semiconductor device and JFET semiconductor device 有权转让
标题翻译： JFET半导体器件和JFET半导体器件的制造方法
公开(公告)号：EP2782122A2
公开(公告)日：2014-09-24
申请号：EP14160755.6
申请日：2014-03-19
申请人： Renesas Electronics Corporation
发明人： Kagotoshi, Yasuaki , Arai, Koichi , Yokoyama, Natsuki , Shimizu, Haruka
IPC分类号： H01L21/337 , H01L29/808
CPC分类号： H01L29/0619 , H01L29/1066 , H01L29/1608 , H01L29/42316 , H01L29/66068 , H01L29/66893 , H01L29/8083
摘要： A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n + -type source layer on a surface of an n - -type drift layer formed on an n + -type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n - -type drift layer with a silicon oxide film formed on the n - -type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n - -type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n - -type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.
摘要翻译：一种结型场效应晶体管的制造方法包括以下步骤：（a）在形成于n +型SiC衬底上的n型漂移层的表面上形成n +型源极层; （b）通过蚀刻n-型漂移层的表面，以形成在n-型漂移层上的氧化硅膜作为掩模，以预定间隔形成多个浅沟槽; （c）通过使用垂直离子注入方法用氮在每个浅沟槽下方掺杂n型漂移层来形成n型计数器掺杂层; （d）在氧化硅膜和浅沟槽的每个侧壁上形成侧壁间隔物; 和（e）通过使用垂直离子注入方法在每个浅沟槽下面用铝掺杂所述n-型漂移层来形成p-型栅极层。

58. 发明公开

EP2779242A1 SCHOTTKY BARRIER DIODE 审中-公开
标题翻译：肖特基BARRIEREN二极管
公开(公告)号：EP2779242A1
公开(公告)日：2014-09-17
申请号：EP12848460.7
申请日：2012-11-08
申请人： Tamura Corporation
发明人： TAKIZAWA, Masaru , KURAMATA, Akito
IPC分类号： H01L29/47 , H01L29/872
CPC分类号： H01L29/24 , H01L21/02414 , H01L21/02433 , H01L21/02565 , H01L21/02576 , H01L21/02631 , H01L29/0619 , H01L29/0661 , H01L29/267 , H01L29/47 , H01L29/66969 , H01L29/872
摘要： Provided is a Schottky barrier diode that is capable of preventing an increase in a forward voltage and an increase in a contact resistance with an ohmic electrode layer even when a reverse withstand voltage is increased. The Schottky barrier diode (1) is provided with: an n-type semiconductor layer (3) comprising Ga 2 O 3 -based compound semiconductors with n-type conductivity; and a Schottky electrode layer (2) which is in Schottky-contact with the n-type semiconductor layer (3). An n - -type semiconductor layer (31), which has a relatively low electron carrier concentration and is brought into Schottky-contact with the Schottky electrode layer (2), and an n + semiconductor layer (32), which has a higher electron carrier concentration than the n - semiconductor layer (31), are formed in the n-type semiconductor layer (3).
摘要翻译：提供了即使当反向耐受电压增加时也能够防止正向电压的增加和与欧姆电极层的接触电阻的增加的肖特基势垒二极管。肖特基势垒二极管（1）设置有：具有n型导电性的包含Ga 2 O 3的化合物半导体的n型半导体层（3）和与n型半导体层（3）肖特基接触的肖特基电极层（2）。具有较低电子载流子浓度并与肖特基电极层（2）肖特基接触的n - 型半导体层（31）和具有较高电子的n +半导体层（32）载流子浓度比n型半导体层（31）形成在n型半导体层（3）中。

59. 发明公开

EP2686876A4 SEMICONDUCTOR DEVICES INCLUDING SCHOTTKY DIODES HAVING OVERLAPPING DOPED REGIONS AND METHODS OF FABRICATING SAME 有权
标题翻译：与用于生产OVERLAPPING掺杂区和过程肖特基二极管半导体器件
公开(公告)号：EP2686876A4
公开(公告)日：2014-09-17
申请号：EP12761339
申请日：2012-03-06
申请人： CREE INC
发明人： ZHANG QINGCHUN , HENNING JASON
IPC分类号： H01L29/872 , H01L21/329 , H01L29/06 , H01L29/24
CPC分类号： H01L29/6606 , H01L21/046 , H01L21/0495 , H01L29/0619 , H01L29/0692 , H01L29/1608 , H01L29/8611 , H01L29/872
摘要： A semiconductor device includes a semiconductor layer having a first conductivity type and having a surface in which an active region of the semiconductor device is defined, and a plurality of spaced apart doped regions within the active region. The plurality of doped regions have a second conductivity type that is opposite the first conductivity type and define a plurality of exposed portions of the semiconductor layer within the active region. The plurality of doped regions include a plurality of rows extending in a longitudinal direction. Each of the rows includes a plurality of longitudinally extending segments, and the longitudinally extending segments in a first row at least partially overlap the longitudinally extending segments in an adjacent row in a lateral direction that is perpendicular to the longitudinal direction.
摘要翻译：一种半导体器件，包括：具有第一导电类型并且具有在其中的表面到半导体器件的有源区被限定的半导体层，和间隔开的掺杂区域的有源区域内的多个。掺杂区域的多元性具有第二导电类型的第一导电性相反所做的是类型和有源区中定义的半导体层的暴露部分的复数。掺杂区域的多元性包括行中沿纵向方向延伸的复数。每一行包括沿纵向延伸的段的多个，并且在第一行中的纵向延伸的段至少部分重叠的纵向在相邻行扩展段中在横向方向上所做的是垂直于纵向的方向。

60. 发明公开

EP2765611A2 Vertical gallium nitride transistors and methods of fabricating the same 审中-公开
标题翻译：垂直氮化镓晶体管及其制造方法
公开(公告)号：EP2765611A2
公开(公告)日：2014-08-13
申请号：EP14152839.8
申请日：2014-01-28
申请人： Seoul Semiconductor Co., Ltd.
发明人： Motonobu, Takeya , Lee, Kwan Hyun , Jong, Young Do , Kwak, June Sik , Lee, Kang Nyung
IPC分类号： H01L29/78 , H01L29/778 , H01L29/06 , H01L21/336 , H01L29/20 , H01L29/04 , H01L29/32 , H01L29/34 , H01L29/417 , H01L21/683
CPC分类号： H01L29/7788 , B82Y10/00 , H01L21/6835 , H01L29/045 , H01L29/0619 , H01L29/0646 , H01L29/0653 , H01L29/0878 , H01L29/122 , H01L29/2003 , H01L29/32 , H01L29/34 , H01L29/41741 , H01L29/41766 , H01L29/41775 , H01L29/42368 , H01L29/66431 , H01L29/66462 , H01L29/66666 , H01L29/66712 , H01L29/66727 , H01L29/66909 , H01L29/7802 , H01L29/7828 , H01L29/802 , H01L29/8083 , H01L2221/6835 , H01L2221/68363 , H01L2221/68381
摘要： Vertical gallium nitride field-effect transistors and corresponding manufacturing methods are provided. A transistor includes a semiconductor structure (20) including a first semiconductor layer (25) of a first conductivity type having a bottom surface and sidewalls, a second semiconductor layer (29) of the first conductivity type surrounding the bottom surface and the sidewalls of the first semiconductor layer, and a semiconductor layer (27) of a second conductivity type disposed between the first semiconductor layer and the second semiconductor layer to separate the first and second semiconductor layers from each other. Current blocking layers (31, 115, 135) may be provided. Other transistors include a heterojunction to provide a two dimensional electron gas (2DEG).
摘要翻译：提供垂直氮化镓场效应晶体管和相应的制造方法。晶体管包括：半导体结构（20），其包括具有底表面和侧壁的第一导电类型的第一半导体层（25），围绕底表面和第一导电类型的侧壁的第一导电类型的第二半导体层（29）第一半导体层以及设置在第一半导体层和第二半导体层之间以将第一和第二半导体层彼此分开的第二导电类型的半导体层（27）。电流阻挡层（31,115,135）可以被提供。其他晶体管包括异质结以提供二维电子气（2DEG）。

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