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41. 发明公开

EP1266054A2 GRADED THIN FILMS 有权
标题翻译：分级薄层
公开(公告)号：EP1266054A2
公开(公告)日：2002-12-18
申请号：EP01918295.5
申请日：2001-03-02
申请人： ASM America, Inc.
发明人： WERKHOVEN, Christiaan, J. , RAAIJMAKERS, Ivo , HAUKKA, Suvi, P.
IPC分类号： C30B25/14 , C23C16/44 , H01L21/205
CPC分类号： H01L21/28185 , C23C16/029 , C23C16/34 , C23C16/401 , C23C16/403 , C23C16/405 , C23C16/452 , C23C16/45529 , C23C16/45531 , C23C16/45534 , C30B25/14 , H01L21/0214 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28194 , H01L21/28202 , H01L21/28562 , H01L21/3141 , H01L21/3145 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/3185 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2221/1089 , H01L2924/0002 , Y10T428/24942 , Y10T428/2495 , H01L2924/00
摘要： Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles (301) or (450, 455, 460, 470) including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources (306 or 460) are introduced during the cyclical process. A graded gate dielectric (72) is thereby provided, even for extremely thin layers. The gate dielectric (72) as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric (72) can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (432) (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses (460) can gradually increase in frequency, forming a graded transition region (434), until pure copper (436) is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces.

42. 发明公开

EP1201790A1 Seed layer 有权
标题翻译： Keimschicht
公开(公告)号：EP1201790A1
公开(公告)日：2002-05-02
申请号：EP01308994.1
申请日：2001-10-23
申请人： Shipley Company LLC
发明人： Merricks, David , Morrissey, Denis , Bayes, Martin w. , Lefebvre, Mark , Shelnut, James G. , Storjohann, Donald E.
IPC分类号： C25D7/12 , C25D5/54 , H01L21/768 , C23C18/30 , C23C18/54
CPC分类号： H01L21/76843 , C23C18/28 , C25D3/38 , C25D5/54 , C25D7/123 , H01L21/288 , H01L21/2885 , H01L21/76868 , H01L21/76873 , H01L21/76877 , H01L2221/1089
摘要： Disclosed are methods for repairing or enhancing discontinuous metal seed layers disposed on a substrate prior to subsequent metallization such as during the manufacture of electronic devices. Such repair methods do not require the use of a second electroplating bath, but comprise the steps of: contacting a metal seed layer disposed on a substrate with a copper colloid composition comprising a minor amount of ionizable palladium compound and a major amount of copper colloid particles to form a substantially continuous seed layer.
摘要翻译：公开了用于修复或增强在随后的金属化之前设置在基板上的不连续金属种子层的方法，例如在制造电子器件期间。这种修复方法不需要使用第二电镀浴，而是包括以下步骤：使设置在基底上的金属种子层与包含少量可电离钯化合物的铜胶体组合物和大量的铜胶体颗粒以形成基本上连续的种子层。

43. 发明公开

EP1199383A2 Seed layer repair bath 审中-公开
标题翻译： Bad zur reparierung einer Keimschicht
公开(公告)号：EP1199383A2
公开(公告)日：2002-04-24
申请号：EP01308870.3
申请日：2001-10-19
申请人： Shipley Company LLC
发明人： Merricks, David , Morrissey, Denis , Bayes, Martin W. , Lefebvre, Mark , Shelnut, James G. , Storjohann, Donald E.
IPC分类号： C25D3/38 , C25D5/48 , C25D7/12 , H01L21/321
CPC分类号： H01L21/76868 , C25D3/38 , C25D5/48 , C25D7/123 , H01L21/2885 , H01L21/76874 , H01L2221/1089 , H05K3/244
摘要： Disclosed are methods for repairing seed layers prior to subsequent metallization during the manufacture of electronic devices.
摘要翻译：公开了在电子设备的制造期间在随后的金属化之前修复种子层的方法。

44. 发明公开

EP0831523A2 Semi-selective chemical vapor deposition of conducting material 失效
标题翻译： Halbselektive化学气相色谱法éleitfähigem材料
公开(公告)号：EP0831523A2
公开(公告)日：1998-03-25
申请号：EP97307355.4
申请日：1997-09-22
申请人： APPLIED MATERIALS, INC.
发明人： Mosely, Roderick Craig , Chen, Lian-Yuh , Guo, Ted
IPC分类号： H01L21/3205 , H01L21/768
CPC分类号： H01L21/76864 , H01L21/76843 , H01L21/76876 , H01L21/76877 , H01L2221/1089 , Y10S977/891
摘要： The disclosure relates to an apparatus and method for semi-selectively depositing a material on a substrate by chemical vapor deposition to form continuous, void-free contact holes or vias in sub-half micron applications. An insulating (22) layer is preferentially deposited on the field of a substrate to delay or inhibit nucleation of metal on the field. A CVD metal (34) is then deposited onto the substrate and grows selectively in the contact hole or via (20) where a barrier layer (22) serves as a nucleation layer. The process is preferably carried out in a multi-chamber system (35) that includes both PVD (36) and CVD (40) processing chambers so that once the substrate is introduced into a vacuum environment, the filing of contact holes and vias occurs without the formation of an oxide layer on a patterned substrate.
摘要翻译：本公开涉及通过化学气相沉积在衬底上半选择性沉积材料以在半微米应用中形成连续的无空隙接触孔或通孔的装置和方法。绝缘（22）层优先沉积在衬底的场上以延迟或抑制场上金属的成核。然后将CVD金属（34）沉积到衬底上并选择性地生长在接触孔或通路（20）中，其中阻挡层（22）用作成核层。该方法优选在包括PVD（36）和CVD（40）处理室的多室系统（35）中进行，使得一旦将基底引入真空环境中，就会发生接触孔和通孔的填充而没有在图案化衬底上形成氧化物层。

45. 发明公开

EP3133637A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD 有权
标题翻译： HERSBLEITERBAUEMENT UND HERSTELLUNGSVERFAHREN
公开(公告)号：EP3133637A1
公开(公告)日：2017-02-22
申请号：EP16191043.5
申请日：2005-10-04
申请人： Fujitsu Semiconductor Limited
发明人： KOURA, Yumiko , KITADA, Hideki , OZAWA, Kiyoshi
IPC分类号： H01L21/288 , H01L21/768 , H01L23/532
CPC分类号： H01L23/53238 , H01L21/2885 , H01L21/76831 , H01L21/76843 , H01L21/76855 , H01L21/76858 , H01L21/76873 , H01L21/76877 , H01L23/5226 , H01L23/53295 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： To manufacture a semiconductor device with copper plugs and/or wirings, the following steps are performed.
(a) A copper alloy film (16, 17) containing at least two metallic elements in addition to copper is formed on the surface of an insulator (31, 41, 51) containing oxygen and formed on a semiconductor substrate (1). (b) A metal film (54a) made of pure copper or copper alloy is formed on the copper alloy film (16, 17). (c) After step (a) or (b), heat treatment is performed under the condition that a metal oxide film (43b, 54b) is formed on a surface of the insulator through reaction between the oxygen in the insulator (31, 41, 51) and the metallic elements in the copper alloy film (16, 17).
摘要翻译：为了制造具有铜插头和/或布线的半导体器件，执行以下步骤。（a）在含氧的绝缘体（31,41,51）的表面上，在半导体基板（1）上形成含有铜以外的至少两种金属元素的铜合金膜（16,17）。（b）在铜合金膜（16,17）上形成由纯铜或铜合金制成的金属膜（54a）。（c）在步骤（a）或（b）之后，在通过绝缘体（31,41）中的氧之间的反应在绝缘体的表面上形成金属氧化物膜（43b，54b）的条件下进行热处理，51）和铜合金膜（16,17）中的金属元素。

46. 发明授权

EP1498511B1 METHOD OF ELECTROLESS PLATING AND SEMICONDUCTOR WAFER HAVING METAL PLATING LAYER FORMED THEREON 有权
标题翻译：方法无电金属沉积和半导体晶片的事实受过训练的金属分离层
公开(公告)号：EP1498511B1
公开(公告)日：2016-07-06
申请号：EP03747201.6
申请日：2003-03-26
申请人： JX Nippon Mining & Metals Corporation
发明人： Imori, Toru , Sekiguchi, Junnosuke , Yabe, Atsushi
IPC分类号： C23C18/28 , H01L21/288 , C23C18/18 , C23C18/16
CPC分类号： H01L21/76874 , C23C18/1844 , C23C18/31 , H01L21/288 , H01L2221/1089

47. 发明公开

EP2224472A4 SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME 有权转让
标题翻译：基板及其制造方法
公开(公告)号：EP2224472A4
公开(公告)日：2012-07-18
申请号：EP08861759
申请日：2008-11-26
申请人： NIPPON MINING CO
发明人： ITO JUNICHI , YABE ATSUSHI , SEKIGUCHI JUNNOSUKE , IMORI TORU
IPC分类号： H01L21/768 , C23C14/00 , C23C14/16 , C23C18/16 , C23C18/18 , C23C18/40 , H01L21/285 , H01L21/288 , H01L21/3205 , H01L23/532
CPC分类号： H01L21/288 , C23C14/0036 , C23C14/165 , C23C18/1601 , C23C18/1637 , C23C18/165 , C23C18/1653 , C23C18/40 , C23C18/54 , H01L21/2855 , H01L21/76843 , H01L21/76874 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00

48. 发明公开

EP2283513A1 STRUCTURE AND PROCESS FOR CONDUCTIVE CONTACT INTEGRATION 审中-公开
标题翻译：结构与工艺集成导电触点
公开(公告)号：EP2283513A1
公开(公告)日：2011-02-16
申请号：EP08823312.7
申请日：2008-09-23
申请人： International Business Machines Corporation
发明人： YANG, Chih-chao , GIGNAC, Lynne M.
IPC分类号： H01L21/02 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76862 , H01L21/76864 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure including a highly reliable high aspect ratio contact structure in which key-hole seam formation is eliminated is provided. The key-hole seam formation is eliminated in the present invention by providing a densified noble metal-containing liner within a high aspect ratio contact opening that is present in a dielectric material. The densified noble metal-containing liner is located atop a diffusion barrier and both those elements separate the conductive material of the inventive contact structure from a conductive material of an underlying semiconductor structure. The densified noble metal-containing liner of the present invention is formed by deposition of a noble metal-containing material having a first resistivity and subjecting the deposited noble metal-containing material to a densification treatment process (either thermal or plasma) that decreases the resistivity of the deposited noble metal-containing material to a lower resistivity.

49. 发明公开

EP1849187A4 WIRING PATTERNS FORMED BY SELECTIVE METAL PLATING 审中-公开
标题翻译：通过选择性金属镀MADE布线图案
公开(公告)号：EP1849187A4
公开(公告)日：2010-11-17
申请号：EP06717977
申请日：2006-01-10
申请人： IBM
发明人： FURUKAWA TOSHIHARU , HAKEY MARK C , HOLMES STEVEN J , HORAK DAVID V , KOBURGER CHARLES W III
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76885 , H01L21/76816 , H01L21/7682 , H01L21/76837 , H01L21/76852 , H01L21/76862 , H01L21/76871 , H01L21/76874 , H01L23/5283 , H01L23/53209 , H01L2221/1089 , H01L2924/0002 , H01L2924/12044 , H01L2924/00

50. 发明公开

EP2142683A2 CONDUCTIVE VIA FORMATION 审中-公开
标题翻译：导电通路的形成
公开(公告)号：EP2142683A2
公开(公告)日：2010-01-13
申请号：EP08762929.1
申请日：2008-06-19
申请人： Cufer Asset Ltd. L.L.C.
发明人： TREZZA, John
IPC分类号： C23C18/16 , C23C18/18 , C23C18/31 , C25D5/02 , C25D7/12
CPC分类号： C25D5/02 , C23C18/1603 , C23C18/165 , C23C18/1653 , H01L21/76868 , H01L21/76873 , H01L21/76898 , H01L2221/1089
摘要： A method involves depositing a first electrically conductive material, using a deposition technique, into a via formed in a material, the via having a diameter at a surface of the material of less than about 10µm and a depth of greater than about 50µm, so as to form a seed layer within the via, then creating a thickening layer on top of the seed layer by electrolessly plating the seed layer with a second electrically conductive material without performing any activation process within the via between via formation and the creating the thickening layer, and then electroplating a conductor metal onto the thickening layer until a volume bounded by the thickening layer within the via is filled with the conductor metal.

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