专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP4377993A1 ENHANCED STRESS TUNING AND INTERFACIAL ADHESION FOR TUNGSTEN (W) GAP FILL 审中-公开
公开(公告)号：EP4377993A1
公开(公告)日：2024-06-05
申请号：EP22850077.3
申请日：2022-07-12
申请人： Applied Materials, Inc.
发明人： CEN, Xi , TAEWOONG, Yun , PETHE, Shirish A. , WU, Kai , SASAKI, Nobuyuki , LEI, Wei
IPC分类号： H01L21/768 , H01L21/285 , H01L23/532
CPC分类号： H01L23/53266 , H01L21/76846 , H01L21/76876 , H01L21/76816

2. 发明公开

EP4328973A3 GATE LINE PLUG STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION 审中-公开
公开(公告)号：EP4328973A3
公开(公告)日：2024-05-29
申请号：EP23220365.3
申请日：2018-10-30
申请人： INTEL Corporation
发明人： HO, Byron , HATTENDORF, Michael L. , AUTH, Christopher P.
IPC分类号： H01L21/8234 , H01L29/66 , H01L29/78 , H01L27/088 , H01L21/033 , H01L21/308 , H01L21/762 , H01L21/768 , H01L21/8238 , H01L23/485 , H01L23/522 , H01L23/532 , H01L27/092 , H01L29/165 , H01L29/417
CPC分类号： H01L21/76883 , H01L21/76885 , H01L21/76897 , H01L23/5226 , H01L23/53209 , H01L23/53238 , H01L21/76801 , H01L21/76816 , H01L21/76834 , H01L21/76846 , H01L21/76849 , H01L29/665 , H01L29/66795 , H01L29/7845 , H01L29/7846 , H01L29/785 , H01L29/165 , H01L29/41791 , H01L29/7848 , H01L29/66545 , H01L27/0886 , H01L21/76232 , H01L21/823431 , H01L21/823821 , H01L21/823842 , H01L21/823871 , H01L21/823878 , H01L27/0924 , H01L28/24 , H01L29/7854 , H01L28/20 , H01L21/823437 , H01L21/823481 , H01L21/823475 , H01L23/485 , H01L2224/7320420130101 , H01L21/3086 , H01L21/0337
摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.

4. 发明授权

EP2360723B1 Semiconductor device with copper wirings and corresponding fabrication method 有权
标题翻译：带有铜布线的半导体器件及相应的制造方法
公开(公告)号：EP2360723B1
公开(公告)日：2018-02-28
申请号：EP11166462.9
申请日：2002-10-09
申请人： Socionext Inc.
发明人： Kakamu, Katsumi , Takao, Yoshihiro
IPC分类号： H01L21/768 , H01L23/532 , H01L21/28 , H01L21/8238 , H01L29/51
CPC分类号： H01L21/76843 , H01L21/28202 , H01L21/76807 , H01L21/76828 , H01L21/76834 , H01L21/76846 , H01L21/823871 , H01L23/53238 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with p-channel MOS transistor having: a gate insulating film (13) of nitrogen-containing silicon oxide; a gate electrode (14) of boron-containing silicon; side wall spacers on side walls of the gate electrode, comprising silicon oxide; an interlayer insulating film (21) having a planarized surface; a wiring trench and a contact via hole formed in the interlayer insulating film; a copper wiring pattern (27) including an underlying barrier layer (26) and an upper level copper region, and filled in the wiring trench; and a silicon carbide layer (29) covering the copper wiring pattern. A semiconductor device has the transistor structure capable of suppressing NBTI deterioration.

5. 发明公开

EP3267478A1 METHOD FOR REDUCING VIA RC DELAY 审中-公开
标题翻译：减少威盛RC延迟的方法
公开(公告)号：EP3267478A1
公开(公告)日：2018-01-10
申请号：EP17179996.8
申请日：2017-07-06
申请人： Semiconductor Manufacturing International Corporation (Beijing) , Semiconductor Manufacturing International Corporation (Shanghai)
发明人： LIU, Jiquan
IPC分类号： H01L23/532 , H01L21/768 , H01L21/285
CPC分类号： H01L21/76883 , H01L21/2855 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76865 , H01L21/76873 , H01L23/5226 , H01L23/53238
摘要： A method for manufacturing an interconnect structure, comprising providing a first metal layer (302) on a substrate, a dielectric layer (304) covering the first metal layer, and an opening (305) extending through the dielectric layer to the first metal layer, the opening having a trench in the upper portion and a through-hole in a lower portion; forming a barrier layer (316) on a bottom and sidewalls of the trench and the through-hole by sputter deposition with a first bias applied to the substrate; forming a second barrier layer (326) by sputter deposition with a second bias applied to the substrate, the second bias being higher than the first bias; removing a portion of the barrier layer on the bottom and on the sidewalls of the trench and the through-hole by bombarding the barrier layer with a plasma with a vertical bias applied to the substrate; and forming a second metal layer filling the opening. In the resulting interconnect structure a sum of thicknesses of the first and second barrier layers on the bottom of the through-hole is less than a sum of thicknesses of the barrier layers on a sidewall of the through-hole.
摘要翻译：一种用于制造互连结构的方法，包括：在衬底上提供第一金属层（302）;覆盖第一金属层的介电层（304）;以及延伸穿过介电层到第一金属层的开口（305）所述开口在上部中具有沟槽并且在下部中具有通孔; 通过溅射沉积在所述沟槽和所述通孔的底部和侧壁上形成阻挡层（316），所述阻挡层具有施加到所述衬底的第一偏压; 通过溅射沉积形成具有施加到衬底的第二偏压的第二阻挡层（326），第二偏压高于第一偏压; 通过用施加垂直偏压的等离子体轰击阻挡层去除沟槽底部和侧壁以及通孔的阻挡层的一部分; 以及形成填充开口的第二金属层。在得到的互连结构中，通孔底部上的第一和第二阻挡层的厚度之和小于通孔侧壁上的阻挡层的厚度之和。

6. 发明公开

EP3264452A1 A SEMICONDUCTOR INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体互连结构及其制造方法
公开(公告)号：EP3264452A1
公开(公告)日：2018-01-03
申请号：EP17178158.6
申请日：2017-06-27
申请人： Semiconductor Manufacturing International Corporation (Beijing) , Semiconductor Manufacturing International Corporation (Shanghai)
发明人： LIU, Jiquan
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/76802 , H01L21/76805 , H01L21/76807 , H01L21/76846 , H01L21/76849 , H01L23/5226 , H01L23/53238
摘要： A semiconductor interconnect structure and its manufacturing method are presented. The manufacturing method includes: providing a substrate structure, wherein the substrate structure comprises: a substrate; a first metal layer on the substrate; a dielectric layer on the substrate, wherein the dielectric layer covers the first metal layer, and wherein the dielectric layer has a hole extending to the first metal layer; and a hard mask layer on the dielectric layer; removing the hard mask layer on the dielectric layer; selectively depositing a second metal layer at the bottom of the hole; and depositing a third metal layer, wherein the third metal layer fills the hole. This semiconductor interconnect structure provides improved reliability over conventional structures.
摘要翻译：介绍了半导体互连结构及其制造方法。该制造方法包括：提供衬底结构，其中衬底结构包括：衬底; 在衬底上的第一金属层; 在所述衬底上的电介质层，其中所述电介质层覆盖所述第一金属层，并且其中所述电介质层具有延伸到所述第一金属层的孔; 以及介电层上的硬掩模层; 去除介电层上的硬掩模层; 在孔的底部选择性沉积第二金属层; 沉积第三金属层，其中第三金属层填充孔。这种半导体互连结构提供了比常规结构更高的可靠性

7. 发明公开

EP3072147A4 MICROELECTRONIC TRANSISTOR CONTACTS AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译： MIKROELEKTRONISCHE TRANSISTORKONTAKTE UND VERFAHREN ZUR HERSTELLUNG DAVON
公开(公告)号：EP3072147A4
公开(公告)日：2017-09-13
申请号：EP13898043
申请日：2013-11-20
申请人： INTEL CORP
发明人： ST AMOUR ANTHONY , STEIGERWALD JOSEPH
IPC分类号： H01L21/768 , H01L23/485 , H01L23/532 , H01L29/78
CPC分类号： H01L23/535 , H01L21/76805 , H01L21/76831 , H01L21/76843 , H01L21/76846 , H01L21/76865 , H01L21/76895 , H01L23/485 , H01L23/5283 , H01L23/53266 , H01L29/6659 , H01L29/7833 , H01L2221/1063 , H01L2924/0002 , H01L2924/00

8. 发明公开

EP3144964A1 SILVER DIFFUSION BARRIER MATERIAL, SILVER DIFFUSION BARRIER, AND SEMICONDUCTOR DEVICE USING SAME 审中-公开
标题翻译：石材加工厂，石材加工厂
公开(公告)号：EP3144964A1
公开(公告)日：2017-03-22
申请号：EP15792649.4
申请日：2015-05-14
申请人： National Institute for Materials Science
发明人： KAWAKITA Jin , HORVATH Barbara , CHIKYO Toyohiro
IPC分类号： H01L21/3205 , C08K3/08 , C08L65/00 , H01L21/768 , H01L23/522 , H01L23/532 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/5384 , C01B21/0823 , C01P2006/40 , C08G61/124 , C08G2261/3221 , C08G2261/51 , C08K3/08 , C08K2003/0806 , C08L65/00 , H01L21/76831 , H01L21/76846 , H01L21/76879 , H01L21/76898 , H01L23/481 , H01L23/53242 , H01L23/5386 , H01L25/065 , H01L25/0657 , H01L25/07 , H01L25/18 , H01L28/00 , H01L29/792 , H01L2225/06544 , H01L2924/0002 , H01L2924/00
摘要： By using silicon oxynitride with an oxygen content of 4.2 to 37.5 at% as a material for a barrier layer, adhesiveness similar to that of silicon oxide and an Ag diffusion prevention property similar to that of silicon nitride can be realized. In particular, in a semiconductor device in which a plurality of silicon chips is vertically stacked by through-silicon vias, Ag is prevented from being diffused into Si and adhesiveness to Si becomes favorable when an Ag/polypyrrole complex is used as a conductive filling material used for the formation of a barrier layer provided on the inner surface of the via.
摘要翻译：通过使用氧含量为4.2〜37.5at％的氧氮化硅作为阻挡层的材料，可以实现与氧化硅类似的粘合性和与氮化硅类似的Ag扩散防止性能。特别地，在通过硅通孔垂直堆叠多个硅芯片的半导体器件中，当Ag /聚吡咯络合物用作导电填充材料时，防止Ag扩散到Si中，并且与Si的粘附性变得有利用于形成设置在通孔的内表面上的阻挡层。

9. 发明公开

EP3067439A1 Electroless metal deposition on a Mn or MnNx barrier 有权
标题翻译： Stromlose Metallabscheidung auf einer Mn Mn，MnNx-Barriere
公开(公告)号：EP3067439A1
公开(公告)日：2016-09-14
申请号：EP15159051.0
申请日：2015-03-13
申请人： IMEC VZW
发明人： Armini, Silvia
IPC分类号： C23C18/12 , C23C18/20
CPC分类号： H01L23/53238 , C23C18/12 , C23C18/20 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L21/76862 , H01L21/76874
摘要： An electronic circuit structure comprising
I. A substrate,
II. A dielectric layer on top of said substrate and comprising a cavity having side-walls,
III. A manganese or manganese nitride layer covering said side-walls, and
IV. A self-assembled monolayer, comprising an organic compound of formula Z-L-A, covering said manganese or manganese nitride layer, wherein Z is selected from the list consisting of a primary amino group, a carboxylic acid group, a thiol group, a selenol group and a heterocyclic group having an unsubstituted tertiary amine in the cycle, wherein L is an organic linker comprising from 1 to 12 carbon atoms and from 0 to 3 heteroatoms, and wherein A is a group attaching the linker to the manganese or manganese nitride layer.
摘要翻译：一种电子电路结构，包括I.A衬底，II。在所述衬底的顶部上的介电层，并且包括具有侧壁的空腔，III。覆盖所述侧壁的锰或氮化锰层，以及IV。一种自组装单层，其包含覆盖所述锰或氮化锰层的式ZLA的有机化合物，其中Z选自伯胺基，羧酸基，硫醇基，硒基和在该循环中具有未取代的叔胺的杂环基，其中L是包含1至12个碳原子和0至3个杂原子的有机连接体，其中A是将连接体连接到锰或氮化锰层的基团。

10. 发明授权

EP2065927B1 Integration and manufacturing method of Cu germanide and Cu silicide as Cu capping layer 有权转让
标题翻译：铜 - 锗和Cu硅化物作为盖的集成和制造方法
公开(公告)号：EP2065927B1
公开(公告)日：2013-10-02
申请号：EP08157374.3
申请日：2008-05-30
申请人： IMEC , Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chung-Shi, Liu Taiwan Semiconductor Manufacturing Company, Ltd. , Chen-Hua, Yu Taiwan Semiconductor Manufacturing Company, Ltd.
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76849 , H01L21/76846 , H01L21/76856 , H01L21/76867 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式