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1. 发明公开

EP0805489A3 Selective via fill using a sacrificial layer 失效
标题翻译：使用牺牲层的接触孔选择填充
公开(公告)号：EP0805489A3
公开(公告)日：1999-02-03
申请号：EP97107036.2
申请日：1997-04-29
申请人： APPLIED MATERIALS, INC.
发明人： Chen, Lian-Yuh , Guo, Ted Tie , Hoinkis, Mark , Mosely, Roderick Craig , Naik, Mehul Bhagubhai , Zhang, Hong
IPC分类号： H01L21/768
CPC分类号： H01L21/76879
摘要： The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron aperture width applications. In one aspect of the invention, a dielectric layer (32) is formed over a conducting member (36). A thin sacrificial layer (34) is then deposited onto the dielectric layer (32) prior to etching high aspect ratio apertures through the sacrificial and dielectric layers (34, 32) to expose the underlying conducting member (36) on the aperture floor (42). A CVD metal layer is then deposited onto the structure (30) to achieve selective deposition within the apertures. The sacrificial film (34) is then etched to remove any nodules (45) formed thereon.

2. 发明公开

EP0831523A2 Semi-selective chemical vapor deposition of conducting material 失效
标题翻译： Halbselektive化学气相色谱法éleitfähigem材料
公开(公告)号：EP0831523A2
公开(公告)日：1998-03-25
申请号：EP97307355.4
申请日：1997-09-22
申请人： APPLIED MATERIALS, INC.
发明人： Mosely, Roderick Craig , Chen, Lian-Yuh , Guo, Ted
IPC分类号： H01L21/3205 , H01L21/768
CPC分类号： H01L21/76864 , H01L21/76843 , H01L21/76876 , H01L21/76877 , H01L2221/1089 , Y10S977/891
摘要： The disclosure relates to an apparatus and method for semi-selectively depositing a material on a substrate by chemical vapor deposition to form continuous, void-free contact holes or vias in sub-half micron applications. An insulating (22) layer is preferentially deposited on the field of a substrate to delay or inhibit nucleation of metal on the field. A CVD metal (34) is then deposited onto the substrate and grows selectively in the contact hole or via (20) where a barrier layer (22) serves as a nucleation layer. The process is preferably carried out in a multi-chamber system (35) that includes both PVD (36) and CVD (40) processing chambers so that once the substrate is introduced into a vacuum environment, the filing of contact holes and vias occurs without the formation of an oxide layer on a patterned substrate.
摘要翻译：本公开涉及通过化学气相沉积在衬底上半选择性沉积材料以在半微米应用中形成连续的无空隙接触孔或通孔的装置和方法。绝缘（22）层优先沉积在衬底的场上以延迟或抑制场上金属的成核。然后将CVD金属（34）沉积到衬底上并选择性地生长在接触孔或通路（20）中，其中阻挡层（22）用作成核层。该方法优选在包括PVD（36）和CVD（40）处理室的多室系统（35）中进行，使得一旦将基底引入真空环境中，就会发生接触孔和通孔的填充而没有在图案化衬底上形成氧化物层。

3. 发明公开

EP0831523A3 Semi-selective chemical vapor deposition of conducting material 失效
标题翻译：导电材料的半选择性化学气相沉积
公开(公告)号：EP0831523A3
公开(公告)日：1999-08-04
申请号：EP97307355.4
申请日：1997-09-22
申请人： APPLIED MATERIALS, INC.
发明人： Mosely, Roderick Craig , Chen, Lian-Yuh , Guo, Ted
IPC分类号： H01L21/3205 , H01L21/768
CPC分类号： H01L21/76864 , H01L21/76843 , H01L21/76876 , H01L21/76877 , H01L2221/1089 , Y10S977/891
摘要： The disclosure relates to an apparatus and method for semi-selectively depositing a material on a substrate by chemical vapor deposition to form continuous, void-free contact holes or vias in sub-half micron applications. An insulating (22) layer is preferentially deposited on the field of a substrate to delay or inhibit nucleation of metal on the field. A CVD metal (34) is then deposited onto the substrate and grows selectively in the contact hole or via (20) where a barrier layer (22) serves as a nucleation layer. The process is preferably carried out in a multi-chamber system (35) that includes both PVD (36) and CVD (40) processing chambers so that once the substrate is introduced into a vacuum environment, the filing of contact holes and vias occurs without the formation of an oxide layer on a patterned substrate.

4. 发明公开

EP0805489A2 Selective via fill using a sacrificial layer 失效
标题翻译： SelektivesAuffüllenvonKontaktlöchernunter Verwendung einer Opferschicht
公开(公告)号：EP0805489A2
公开(公告)日：1997-11-05
申请号：EP97107036.2
申请日：1997-04-29
申请人： APPLIED MATERIALS, INC.
发明人： Chen, Lian-Yuh , Guo, Ted Tie , Hoinkis, Mark , Mosely, Roderick Craig , Naik, Mehul Bhagubhai , Zhang, Hong
IPC分类号： H01L21/768
CPC分类号： H01L21/76879
摘要： The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron aperture width applications. In one aspect of the invention, a dielectric layer (32) is formed over a conducting member (36). A thin sacrificial layer (34) is then deposited onto the dielectric layer (32) prior to etching high aspect ratio apertures through the sacrificial and dielectric layers (34, 32) to expose the underlying conducting member (36) on the aperture floor (42). A CVD metal layer is then deposited onto the structure (30) to achieve selective deposition within the apertures. The sacrificial film (34) is then etched to remove any nodules (45) formed thereon.
摘要翻译：本发明一般涉及一种改进的装置和方法，用于在衬底上提供均匀的台阶覆盖和金属层的平坦化，以形成在半微米孔径宽度应用中的连续的无空隙触点或通孔。在本发明的一个方面中，在导电构件（36）之上形成介电层（32）。然后在蚀刻通过牺牲和电介质层（34,32）的高纵横比孔径之前，将薄的牺牲层（34）沉积到电介质层（32）上，以暴露孔底板（42）上的下面的导电构件）。然后将CVD金属层沉积到结构（30）上以实现孔内的选择性沉积。然后蚀刻牺牲膜（34）以除去其上形成的任何结节（45）。

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