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131. 发明公开

EP2688104A4 SEMICONDUCTOR DEVICE 有权转让
标题翻译： HALBLEITERBAUELEMENT
公开(公告)号：EP2688104A4
公开(公告)日：2014-01-22
申请号：EP11860946
申请日：2011-03-15
申请人： TOYOTA MOTOR CO LTD
发明人： SENOO MASARU
IPC分类号： H01L29/423 , H01L21/336 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/4238 , H01L29/7397
摘要： A first semiconductor device comprising: a first conductivity type drift region formed in a semiconductor substrate; a second conductivity type body region formed at an upper surface of the semiconductor substrate on an upper surface side of the drift region; a first conductivity type first semiconductor region formed on a part of an upper surface of the body region; and a trench gate type insulated gate penetrating the first semiconductor region and the body region, and formed to a depth at which the insulated gate contacts the drift region. A part of the insulated gate on a drift region side relative to the body region is deeper at a center portion than at both end portions in a longitudinal direction of the insulated gate.
摘要翻译：第一半导体器件，包括：形成在半导体衬底中的第一导电型漂移区; 第二导电类型体区，形成在漂移区的上表面侧上的半导体衬底的上表面处; 第一导电类型的第一半导体区域，形成在本体区域的上表面的一部分上; 以及贯穿所述第一半导体区域和所述本体区域并形成到所述绝缘栅极接触所述漂移区域的深度的沟槽栅极型绝缘栅极。相对于体区的漂移区侧的绝缘栅的一部分在绝缘栅的长度方向的中央部分比在两端部分深。

132. 发明公开

EP2482320A3 Method of fabricating a deep trench insulated gate bipolar transistor 审中-公开
标题翻译：制造深沟槽绝缘栅双极晶体管的方法
公开(公告)号：EP2482320A3
公开(公告)日：2013-12-04
申请号：EP12164824.0
申请日：2009-12-18
申请人： Power Integrations, Inc.
发明人： Parthasarathy, Vijay , Banerjee, Sujit
IPC分类号： H01L29/739 , H01L21/331 , H01L29/66
CPC分类号： H01L29/7397 , H01L29/66333
摘要： In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.
摘要翻译：在一个实施例中，一种方法包括在相反导电类型的衬底之上形成外延层，所述外延层被具有在垂直方向上基本上恒定的掺杂浓度的缓冲层分隔到缓冲层。在外延层中从外延层的顶表面至少向下到缓冲层中形成一对间隔开的沟槽。介电材料形成在第一和第二侧壁部分上方的沟槽中。在外延层的顶部形成源极/集电极和本体区，本体区将柱的源极/集电极区与从本体区延伸到缓冲层的外延层的漂移区分隔开。然后在与本体区域相邻并绝缘的每个沟槽中形成绝缘门构件。

133. 发明公开

EP2667418A2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：EP2667418A2
公开(公告)日：2013-11-27
申请号：EP13168372.4
申请日：2013-05-17
申请人： Fuji Electric Co., Ltd.
发明人： Koyama, Hiromi , Shiigi, Takashi , Fukuchi Akihiro , Momoto, Seiji , Matsui, Toshiyuki
IPC分类号： H01L29/78 , H01L29/739 , H01L29/861 , H01L29/06 , H01L29/40
CPC分类号： H01L29/7393 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/0692 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/7397 , H01L29/7811 , H01L29/8611
摘要： Provided is a semiconductor device capable of obtaining a high reverse recovery resistant amount by allowing sheet resistance of a peripheral portion in a p type diffusion region which is in contact with a metal electrode through an insulating film on a surface to be as high as possible and reducing an increase in cost if possible. The semiconductor device includes: a p type diffusion region which is arranged in a surface layer of the one main surface of an n type semiconductor substrate; and a voltage-resistant region which surrounds the p type diffusion region, wherein the p type diffusion region includes: an active region which is covered with a metal electrode which is in ohmic contact with a surface thereof; and a ring-shaped peripheral portion which surrounds the active region and includes an insulating film on a surface thereof, and wherein the peripheral portion includes a p type diffusion region extension portion which is selectively diffused so as to increase sheet resistance between an inner circumferential end and an outer circumferential end of the ring-shaped peripheral portion.
摘要翻译：本发明提供一种半导体装置，其能够通过使表面上的绝缘膜与金属电极接触的p型扩散区域中的周边部分的表面电阻尽可能高并且降低表面电阻而获得高的反向恢复抵抗量尽可能增加成本。该半导体器件包括：p型扩散区，其布置在n型半导体衬底的一个主表面的表面层中; 以及包围所述p型扩散区域的耐压区域，所述p型扩散区域包含：被与表面欧姆接触的金属电极覆盖的有源区域; 以及环形周边部分，所述环形周边部分围绕所述有源区域并且在其表面上包括绝缘膜，并且其中所述周边部分包括p型扩散区域延伸部分，所述p型扩散区域延伸部分被选择性地扩散以增加内部圆周端部和该环形周边部分的外周端。

134. 发明公开

EP2662897A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：EP2662897A1
公开(公告)日：2013-11-13
申请号：EP11854692.8
申请日：2011-12-07
申请人： Sumitomo Electric Industries, Ltd.
发明人： HIYOSHI, Toru , MASUDA, Takeyoshi
IPC分类号： H01L29/78 , H01L21/28 , H01L21/316 , H01L21/3205 , H01L21/336 , H01L29/12 , H01L29/739
CPC分类号： H01L29/7802 , H01L21/0475 , H01L29/1608 , H01L29/66068
摘要： A method of manufacturing a MOSFET (100) includes the steps of preparing a silicon carbide substrate (1), forming an active layer (7) on the silicon carbide substrate (1), forming a gate oxide film (91) on the active layer (7), forming a gate electrode (93) on the gate oxide film (91), forming a source contact electrode (92) on the active layer (7), and forming a source interconnection (95) on the source contact electrode (92). The step of forming the source interconnection (95) includes the steps of forming a conductor film on the source contact electrode (92) and processing the conductor film by etching the conductor film with reactive ion etching. Then, the method of manufacturing a MOSFET 100 further includes the step of performing annealing of heating the silicon carbide substrate (1) to a temperature not lower than 50°C after the step of processing the conductor film.
摘要翻译：一种制造MOSFET（100）的方法包括以下步骤：准备碳化硅衬底（1）;在碳化硅衬底（1）上形成有源层（7）;在有源层上形成栅极氧化物膜（91）（7）上，在栅氧化膜（91）上形成栅电极（93），在有源层（7）上形成源极接触电极（92），并在源极接触电极上形成源极互连（95） 92）。形成源极互连（95）的步骤包括在源极接触电极（92）上形成导体膜并通过用反应离子蚀刻蚀刻导体膜来处理导体膜的步骤。然后，制造MOSFET 100的方法还包括在处理导体膜的步骤之后执行将碳化硅衬底（1）加热到不低于50℃的温度的退火的步骤。

135. 发明公开

EP2657958A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译： HERSTELLUNGSVERFAHRENFÜREINE HALBLEITERVORRICHTUNG
公开(公告)号：EP2657958A1
公开(公告)日：2013-10-30
申请号：EP10859503.4
申请日：2010-11-10
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA
发明人： TANIDA Atsushi
IPC分类号： H01L21/336 , H01L21/322 , H01L21/76 , H01L27/04 , H01L29/06 , H01L29/739 , H01L29/78 , H01L29/861
CPC分类号： H01L29/32 , B23K26/0006 , B23K26/0057 , B23K2203/56 , H01L21/268 , H01L21/761 , H01L29/0619 , H01L29/7397 , H01L29/8611
摘要： A method for manufacturing a semiconductor device includes irradiating light to an effective region of a semiconductor substrate. A wavelength of the light is a wavelength adapted so that light absorptance of the semiconductor substrate increases if an intensity of the light increases. The light is irradiated so that a focus point of the light is made within the semiconductor substrate in the irradiating.
摘要翻译：一种制造半导体器件的方法包括：将光照射到半导体衬底的有效区域。光的波长是适于使得如果光的强度增加则半导体衬底的光吸收率增加的波长。照射光，使得在照射下在半导体衬底内形成光的聚焦点。

136. 发明授权

EP1883102B1 Method for improving the quality of an SiC crystal and SiC semiconductor device 有权
标题翻译：一种用于改善SiC晶体质量的方法，以及SiC半导体装置。
公开(公告)号：EP1883102B1
公开(公告)日：2013-10-02
申请号：EP06255833.3
申请日：2006-11-15
申请人： Central Research Institute of Electric Power Industry
发明人： Tsuchida, Hidekazu Materials Science Research Lab. , Storasta, Liutauras Materials Science Res. Lab.
IPC分类号： H01L21/04 , H01L21/265 , H01L29/24 , H01L21/322 , H01L29/732 , H01L29/74 , H01L29/861 , H01L29/739
CPC分类号： H01L21/0445 , C30B29/36 , C30B31/22 , H01L21/322 , H01L29/16 , H01L29/1608 , H01L29/7325 , H01L29/7395

137. 发明公开

EP2637210A1 Power semiconductor device and method for manufacturing thereof 审中-公开
标题翻译： Leistungshalbleiterbauelement和Verfahren zu seiner Herstellung
公开(公告)号：EP2637210A1
公开(公告)日：2013-09-11
申请号：EP12158043.5
申请日：2012-03-05
申请人： ABB Technology AG
发明人： Rahimo, Munaf , Corvasce, Chiara , Vobecky, Jan , Otani, Yoichi
IPC分类号： H01L29/08 , H01L29/45 , H01L29/739 , H01L29/861
CPC分类号： H01L29/66325 , H01L21/2251 , H01L21/283 , H01L21/324 , H01L29/0834 , H01L29/45 , H01L29/456 , H01L29/6609 , H01L29/66136 , H01L29/66333 , H01L29/66348 , H01L29/7395 , H01L29/7397 , H01L29/8613
摘要： A method for manufacturing a power semiconductor device is provided comprising the following steps:
- providing a wafer (1) of a first conductivity type, which wafer has a first main side (11) and a second main side (15) opposite to the first main side (11),
- applying on the second main side (15) at least one of a dopant of the first conductivity type for forming a layer (2) of the first conductivity type and a dopant of a second conductivity type for forming a layer (2) of the second conductivity type,
- afterwards depositing a metal deposition layer (3) with a metal having a melting point above 1300 °C on the second main side (15),
- annealing the metal deposition layer (3) so that simultaneously an intermetal compound layer (35) is formed at the interface between the metal deposition layer (3) and the wafer (1) and the dopant is diffused into the wafer (1),
- creating a first metal electrode layer (4) on the second side (15).
摘要翻译：提供了一种用于制造功率半导体器件的方法，包括以下步骤： - 提供第一导电类型的晶片（1），该晶片具有第一主侧（11）和与第一导电类型相反的第二主侧（15）主侧（11）， - 在第二主侧（15）上施加第一导电类型的掺杂剂中的至少一种，用于形成第一导电类型的层（2）和用于形成第一导电类型的第二导电类型的掺杂剂第二导电类型的层（2），然后在第二主侧（15）上沉积具有高于1300℃的熔点的金属的金属沉积层（3）， - 使金属沉积层（3）退火同时在金属沉积层（3）和晶片（1）之间的界面处形成金属间化合物层（35），并且掺杂剂扩散到晶片（1）中，产生第一金属电极层（4）在第二面（15）。

138. 发明公开

EP2631951A3 High power insulated gate bipolar transistors 有权
标题翻译：高功率绝缘栅双极型晶体管
公开(公告)号：EP2631951A3
公开(公告)日：2013-09-04
申请号：EP13169099.2
申请日：2007-06-18
申请人： Cree, Inc.
发明人： The designation of the inventor has not yet been filed
IPC分类号： H01L29/739 , H01L21/04
CPC分类号： H01L29/66068 , H01L21/02378 , H01L21/02529 , H01L21/046 , H01L21/049 , H01L21/2254 , H01L21/26513 , H01L21/324 , H01L29/1095 , H01L29/1608 , H01L29/66333 , H01L29/7395
摘要： An insulated gate bipolar transistor, comprising:
a substrate having a first conductivity type;
a drift layer having a second conductivity type opposite the first conductivity type;
a well region in the drift layer and having the first conductivity type;
a epitaxial channel adjustment layer on the drift layer and having the second conductivity type and having a thickness of about 0.25 µm or more;
an emitter region extending from a surface of the epitaxial channel adjustment layer through the epitaxial channel adjustment layer and into the well region, the emitter region having the second conductivity type and at least partially defining a channel region in the well region adjacent to the emitter region;
a gate oxide layer on the channel region; and
a gate on the gate oxide layer.
摘要翻译：一种绝缘栅双极晶体管，包括：具有第一导电类型的衬底; 具有与第一导电类型相反的第二导电类型的漂移层; 在漂移层中具有第一导电类型的阱区; 外延沟道调整层，位于所述漂移层上并且具有所述第二导电类型并且具有大约0.25μm或更大的厚度; 发射极区域，其从所述外延沟道调节层的表面延伸穿过所述外延沟道调节层并进入所述阱区域，所述发射极区域具有所述第二导电类型并且至少部分地限定所述阱区域中与所述发射极区域相邻的沟道区域 ; 沟道区上的栅极氧化物层; 和栅氧化层上的栅极。

139. 发明公开

EP2387077A3 Semiconductor device with a peripheral base region 审中-公开
标题翻译： Halibiteranordnung mit einem Peripheriebasisbereich
公开(公告)号：EP2387077A3
公开(公告)日：2013-08-21
申请号：EP11174233.4
申请日：2001-04-04
申请人： Mitsubishi Denki Kabushiki Kaisha
发明人： Hatade, Kazunari , Hisamoto, Yoshiaki
IPC分类号： H01L29/78 , H01L29/739 , H01L29/10 , H01L29/08 , H01L21/336 , H01L29/06 , H01L29/40
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0619 , H01L29/0626 , H01L29/063 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/42368 , H01L29/66712 , H01L29/7395 , H01L29/7805 , H01L29/7808 , H01L29/7813
摘要： The present invention relates to a semiconductor device and has an object to enhance a di / dt tolerance and a dV / dt tolerance without increasing an ON resistance.
In order to achieve the object described above, the semiconductor device has a peripheral base region (21) formed in a drain layer (3) of opposite conductivity type. Said peripheral base region may be coupled to one end of regions of a main base region (4).
摘要翻译：本发明涉及一种半导体器件，其目的是在不增加导通电阻的情况下提高di / dt公差和dV / dt公差。为了实现上述目的，设置在设置在栅极焊盘（12）下方的半导体衬底（1）的上主表面上的区域上的底板基区（5）不连接到源极（ 11），并且不耦合到连接到源电极（11）的主基区（4）。更具体地，底板底座区域（5）进入浮动状态。

140. 发明公开

EP2615642A1 Trench-gate MISFET 审中-公开
标题翻译：晶体管屏蔽器A-Seiten-Leitkanal和Grabenschutzbohrbereich
公开(公告)号：EP2615642A1
公开(公告)日：2013-07-17
申请号：EP13161683.1
申请日：2008-12-05
申请人： Cree, Inc.
发明人： Zhang, Qingchun , Agarwal, Anant , Jonas, Charlotte
IPC分类号： H01L29/04 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78 , H01L29/739 , H01L29/749 , H01L29/24
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0615 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/749 , H01L29/7828
摘要： A transistor (50) has an insulated control contact (61) within a trench (56). The transistor comprises a pair of semiconductor mesas (65) defining the trench, each semiconductor mesa of the pair of semiconductor mesas comprising at least one p-n junction. A drift layer (55) of a first conductivity type extends between the pair of semiconductor mesas and beneath the trench. A first doped well (77) of a second conductivity type extends from a first semiconductor mesa of the pair of semiconductor mesas to a depth within the drift layer that is greater than a depth of the trench. A source contact (60) is in direct contact with the first doped well.
摘要翻译：晶体管（50）在沟槽（56）内具有绝缘控制触点（61）。晶体管包括限定沟槽的一对半导体台面（65），该对半导体台面的每个半导体台面包括至少一个p-n结。第一导电类型的漂移层（55）在该对半导体台面之间和沟槽之下延伸。第二导电类型的第一掺杂阱（77）从一对半导体台面的第一半导体台面延伸到漂移层内比沟槽深度大的深度。源触点（60）与第一掺杂阱直接接触。

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