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111. 发明公开

EP2979268A4 LOW-POWER, HIGH-ACCURACY CURRENT REFERENCE FOR HIGHLY DISTRIBUTED CURRENT REFERENCES FOR CROSS POINT MEMORY 有权
标题翻译：高精度低功耗电流参考强有力的分布式电源参考有关的交叉点存储器
公开(公告)号：EP2979268A4
公开(公告)日：2017-03-15
申请号：EP14774639
申请日：2014-02-13
申请人： INTEL CORP
发明人： DAYLEY MATTHEW G , VANCHA YADHU VAMSHI S
IPC分类号： G11C5/14 , G11C7/10
CPC分类号： G11C5/147 , G05F3/08 , G05F3/26 , G11C7/10 , G11C7/14 , G11C27/02 , G11C27/024
摘要： A highly distributed current reference for a solid-state memory comprises a centrally located current digital-to-analog converter (IDAC) and a plurality of remotely located tile current references. The IDAC comprises a first active device that generates a reference current, and a device that forms a first source degeneration resistance for the first active device. The IDAC outputs a voltage signal that represents a magnitude of the reference current. A remotely located tile current reference comprises a second active device and a device that forms a second source degeneration resistance for the second active device. The source degeneration resistances and capacitance coupled to the voltage signal output from the IDAC compensate for current, temperature, supply and process variations.

112. 发明公开

EP3043350A3 MEMORY DEVICE WITH DATA VALIDITY CHECK 审中-公开
标题翻译： SPEICHERVORRICHTUNG MITDATENGÜLTIGKEITSKONTROLLE
公开(公告)号：EP3043350A3
公开(公告)日：2017-01-11
申请号：EP15199840.8
申请日：2015-12-14
申请人： Delphi Technologies, Inc.
发明人： BORING, Jeffrey, Todd
IPC分类号： G11C5/00 , G11C7/24 , G11C29/24 , G11C29/52 , G11C16/34 , G11C7/14
CPC分类号： G11C29/04 , G11C5/005 , G11C7/14 , G11C7/24 , G11C13/0004 , G11C13/0021 , G11C16/349 , G11C29/24 , G11C29/52 , G11C2029/0409
摘要： A memory device (10) for storing data includes a memory cell (14) and a test cell (16). The memory cell (14) is configured to indicate a data value based on a threshold voltage of the memory cell (14). The test cell (16) is configured to indicate a validity rating of the data value stored in the memory cell (14). The validity rating is determined after exposure to an environmental condition such as high temperatures and/or X-ray radiation. The validity rating is based on a test shift (22) from an initial threshold voltage of the test cell (16) prior to exposure to the environmental condition to a shifted threshold voltage of the test cell (16) after exposure to the environmental condition. The validity rating is characterized as invalid when the test shift (22) is greater than a threshold value.
摘要翻译：用于存储数据的存储器件（10）包括存储器单元（14）和测试单元（16）。存储单元（14）被配置为基于存储单元（14）的阈值电压来指示数据值。测试单元（16）被配置为指示存储在存储单元（14）中的数据值的有效性等级。有效性等级在暴露于诸如高温和/或X射线辐射的环境条件之后确定。有效性等级基于在暴露于环境条件之后从暴露于环境条件到测试电池（16）的偏移阈值电压的测试电池（16）的初始阈值电压的测试移位（22）。当测试偏移（22）大于阈值时，有效性等级被表征为无效。

113. 发明公开

EP3043350A2 MEMORY DEVICE WITH DATA VALIDITY CHECK 审中-公开
标题翻译：与数据存储设备适用于防治
公开(公告)号：EP3043350A2
公开(公告)日：2016-07-13
申请号：EP15199840.8
申请日：2015-12-14
申请人： Delphi Technologies, Inc.
发明人： BORING, Jeffrey, Todd
IPC分类号： G11C5/00 , G11C7/24 , G11C29/24 , G11C29/52
CPC分类号： G11C29/04 , G11C5/005 , G11C7/14 , G11C7/24 , G11C13/0004 , G11C13/0021 , G11C16/349 , G11C29/24 , G11C29/52 , G11C2029/0409
摘要： A memory device (10) for storing data includes a memory cell (14) and a test cell (16). The memory cell (14) is configured to indicate a data value based on a threshold voltage of the memory cell (14). The test cell (16) is configured to indicate a validity rating of the data value stored in the memory cell (14). The validity rating is determined after exposure to an environmental condition such as high temperatures and/or X-ray radiation. The validity rating is based on a test shift (22) from an initial threshold voltage of the test cell (16) prior to exposure to the environmental condition to a shifted threshold voltage of the test cell (16) after exposure to the environmental condition. The validity rating is characterized as invalid when the test shift (22) is greater than a threshold value.

114. 发明公开

EP2569775A4 DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS 有权
标题翻译： BESTIMMUNG UND VERWENDUNG WEICHER DATEN IN SPEICHERVORRICHTUNGEN UND -SYSTEMEN
公开(公告)号：EP2569775A4
公开(公告)日：2015-06-10
申请号：EP11780905
申请日：2011-05-02
申请人： MICRON TECHNOLOGY INC
发明人： RADKE WILLIAM H , SHEN ZHENLEI , FEELEY PETER
IPC分类号： G11C16/34 , G11C7/14 , G11C11/56 , G11C16/06 , G11C29/02 , G11C29/42 , G11C29/50
CPC分类号： G11C16/26 , G11C7/14 , G11C11/26 , G11C11/5628 , G11C11/5642 , G11C16/349 , G11C29/021 , G11C29/028 , G11C29/42 , G11C29/50004
摘要： The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data.
摘要翻译：本公开包括用于在存储器设备和系统中确定和使用软数据的方法，设备和系统。一个或多个实施例包括耦合到阵列的存储器单元阵列和控制电路。控制电路被配置为使用多个感测电压对存储器单元执行多个感测操作，以确定与存储器单元的目标状态相关联的软数据，并且基于以下方式调整用于确定目标状态的感测电压：最少部分地在确定的软数据上。

115. 发明公开

EP2380175A1 BALANCING A SIGNAL MARGIN OF A RESISTANCE BASED MEMORY CIRCUIT 有权
标题翻译：克服了信号预留存储器电路电阻的基层
公开(公告)号：EP2380175A1
公开(公告)日：2011-10-26
申请号：EP09802075.3
申请日：2009-12-18
申请人： QUALCOMM Incorporated
发明人： JUNG, Seong-Ook , KIM, Jisu , SONG, Jee-Hwan , KANG, Seung H. , YOON, Sei Seung , SANI, Mehdi Hamidi
IPC分类号： G11C11/16 , G11C7/06
CPC分类号： G11C7/14 , G11C7/12 , G11C11/1673
摘要： A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure. The bit line is adapted to detect data having a logic one value when the bit line has a first voltage value, and to detect data having a logic zero value when the bit line has a second voltage value. The circuit further includes a second transistor load of a reference cell. The second transistor load is coupled to the first transistor load, and the second transistor load has an associated reference voltage value. A characteristic of the first transistor load, such as transistor width, is adjustable to modify the first voltage value and the second voltage value without substantially changing the reference voltage value.

116. 发明公开

EP1665275A4 METHOD AND APPARATUS FOR READ BITLINE CLAMPING FOR GAIN CELL DRAM DEVICES 有权转让
标题翻译：方法和设备，用于读取位线线夹增益单元DRAM积木
公开(公告)号：EP1665275A4
公开(公告)日：2008-12-24
申请号：EP04821590
申请日：2004-08-25
申请人： IBM
发明人： KIRIHATA TOSHIAKI
IPC分类号： G11C7/00 , G11C7/12 , G11C7/14 , G11C11/405 , G11C11/4094 , G11C11/4099
CPC分类号： G11C11/405 , G11C7/12 , G11C7/14 , G11C11/4094 , G11C11/4099
摘要： A dynamic random access memory (DRAM) storage device includes a storage cell having a plurality of transistors arranged in a gain cell configuration, the gain cell coupled to a read bitline and a write bitline. A dummy cell is configured as a clamping device for the read bitline, wherein the dummy cell opposes a read bitline voltage swing during a read operation of the storage cell.

117. 发明授权

EP1606821B1 AN APPARATUS AND METHOD FOR A CONFIGURABLE MIRROR FAST SENSE AMPLIFIER 有权
标题翻译：装置和方法可配置明镜快速读放大器
公开(公告)号：EP1606821B1
公开(公告)日：2008-10-08
申请号：EP04711923.5
申请日：2004-02-17
申请人： ATMEL CORPORATION
发明人： BEDARIDA, Lorenzo , SACCO, Andrea , MARZIANI, Monica
IPC分类号： G11C11/34 , G11C16/28
CPC分类号： G11C16/28 , G11C7/062 , G11C7/14 , G11C2207/063 , G11C2207/2254
摘要： A configurable mirror sense amplifier system for flash memory having the following features. A power source generates a reference voltage. A plurality of transistors is biased at the reference voltage. The plurality of transistors is each coupled to a second transistor. Each of the plurality of transistors is also configured to provide a current for comparison with the flash memory. The reference voltage is internal, stable and independent from variations of a power supply or temperature. The plurality of transistors is in parallel with one another. A mirror transistor is coupled to the plurality of transistors. The plurality of transistors is configured so that at least one of at least one transistor is activated with a signal in order to provide the current for comparison to the flash memory. Also, the reference voltage may be modified in order to modify the current for comparison to the flash memory.

118. 发明授权

EP1560221B1 Semiconductor memory device 有权
标题翻译：半导体存储装置
公开(公告)号：EP1560221B1
公开(公告)日：2008-09-03
申请号：EP05250434.7
申请日：2005-01-27
申请人： Sharp Kabushiki Kaisha
发明人： Inoue, Koji , Morikawa, Yoshinao , Shimaoka, Atsushi , Tamai, Yukio
IPC分类号： G11C7/06 , G11C7/12
CPC分类号： G11C7/062 , G11C7/06 , G11C7/12 , G11C7/14 , G11C8/08

119. 发明授权

EP1460637B1 Temperature compensated resistive RAM (RRAM) circuit 有权转让
标题翻译：一个电阻器的温度补偿的具有RAM存储器单元
公开(公告)号：EP1460637B1
公开(公告)日：2008-04-30
申请号：EP04251390.3
申请日：2004-03-10
申请人： Sharp Kabushiki Kaisha
发明人： Hsu, Sheng Teng
IPC分类号： G11C7/10 , G11C7/06 , G11C11/14 , G11C11/22 , G11C11/34 , G11C16/02
CPC分类号： G11C13/004 , G11C7/04 , G11C7/062 , G11C7/067 , G11C7/14 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C2013/0054 , G11C2213/31 , G11C2213/72 , G11C2213/79

120. 发明公开

EP1788576A3 A reference cell scheme for MRAM 审中-公开
标题翻译：对于MRAM存储器参考单元方案
公开(公告)号：EP1788576A3
公开(公告)日：2007-10-31
申请号：EP06392014.4
申请日：2006-11-07
申请人： MagIC Technologies Inc. , Applied Spintronics, Inc.
发明人： Hsu Kai Yang , Po-Kang Wang , Xizeng Shi
IPC分类号： G11C11/15 , G11C11/16 , G11C7/14
CPC分类号： G11C7/14 , G11C11/16
摘要： An MRAM reference cell sub-array provides a mid-point reference current to sense amplifiers. The MRAM reference cell sub-array has MRAM cells arranged in rows and columns. Bit lines are associated with each column of the sub-array. A coupling connects the bit lines of pairs of the columns together at a location proximally to the sense amplifiers. The MRAM cells of a first of the pair of columns are programmed to a first magneto-resistive state and the MRAM cells of a second of the pair of columns are programmed to a second magneto-resistive state. When one row of data MRAM cells is selected for reading, a row of paired MRAM reference cells are placed in parallel to generate the mid-point reference current for sensing. The MRAM reference sub-array may be programmed electrically or aided by a magnetic field. A method for verifying programming of the MRAM reference sub-array is discussed.

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