专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP3174201A1 SWITCH USED IN PROGRAMMABLE GAIN AMPLIFIER AND PROGRAMMABLE GAIN AMPLIFIER 审中-公开
标题翻译：开关，可使用在可编程放大器和可编程放大器
公开(公告)号：EP3174201A1
公开(公告)日：2017-05-31
申请号：EP16207064.3
申请日：2010-10-21
申请人： Atmel Corporation
发明人： WEI, Changming , ZHANG, Yu , JIANG, Lixin , CHEN, Jinfu , BARROW, Jeffrey G.
IPC分类号： H03G3/20 , H02M1/08 , H03K17/06 , H03K17/687
CPC分类号： H03F3/45475 , H03F2203/45534 , H03F2203/45536 , H03G1/0088 , H03K17/063 , H03K17/6872 , H03K17/6877 , H03K2017/066 , H03K2217/0054
摘要： A switch circuit is provided. The switch circuit may include a first transistor having a source terminal to accept an input signal, a drain terminal to provide an output signal, and a gate; a power supply providing a gate voltage. The switch circuit may also include a circuit to couple a switch signal to the gate, wherein the circuit turns the first transistor 'off' for all values of the input signal when the switch signal is 'low.' A programmable gain amplifier (PGA) is also provided. The PGA may include an input stage having an input node to couple an input signal, and an output node to provide a gate signal, at least a first gain stage including a resistor and a switch circuit as above. A differential gain amplifier may be included to provide an output signal from the gain signal.
摘要翻译：本发明提供一种开关电路。开关电路可以包括具有源极端接受输入信号，漏极端子，以提供输出信号，和一个栅极的第一晶体管; 一个电源提供的栅极电压。因此，该开关电路可以包括电路耦合的开关信号到栅极，worin接通电路的输入信号。当开关信号是所有值的第一晶体管“关断”“低”。因此，一个可编程增益放大器（PGA）设置。该PGA可以包括在输入级具有输入节点耦合到输入信号，并且输出节点以提供栅极信号，至少包括电阻器和如上述的开关电路的第一增益级。差动增益放大器可被包括以提供对从所述信号增益输出信号。

2. 发明授权

EP1614027B1 EFFICIENT MULTIPLICATION SEQUENCE FOR LARGE INTEGER OPERANDS WIDER THAN THE MULTIPLIER HARDWARE 有权转让
标题翻译：的高效乘法序列的大整数操作数宽于ARE MULTIPLIZIERERHARDWARE
公开(公告)号：EP1614027B1
公开(公告)日：2009-09-09
申请号：EP04759716.6
申请日：2004-03-22
申请人： ATMEL CORPORATION
发明人： DUPAQUIS, Vincent , PARIS, Laurent
IPC分类号： G06F7/52 , G06F9/345
CPC分类号： G06F7/5324 , G06F9/30014 , G06F9/325 , G06F9/3885 , G06F9/3893

3. 发明公开

EP2052344A2 BI-PROCESSOR ARCHITECTURE FOR SECURE SYSTEMS 有权转让
标题翻译： BIPROZESSOR-ARCHITEKTURFÜRSICHERE SYSTEME
公开(公告)号：EP2052344A2
公开(公告)日：2009-04-29
申请号：EP07868330.7
申请日：2007-08-14
申请人： Atmel Corporation
发明人： KAABOUCH, Majid , LE COCQUEN, Eric
IPC分类号： G06F21/00
CPC分类号： G06F21/556 , G06F21/74 , G06F21/75 , G06F21/77
摘要： Systems, methods and program products for a first central processing unit (CPU) configured to perform tasks that do not require manipulation of sensitive information and a second CPU that is configured to perform tasks that manipulate the sensitive information on behalf of the first CPU. The first CPU and the second CPU can communicate through a secure interface. The first CPU cannot access the sensitive information within the second CPU.
摘要翻译：被配置为执行不需要操纵敏感信息的任务的第一中央处理单元（CPU）的系统，方法和程序产品以及被配置为执行代表第一CPU操纵敏感信息的任务的第二CPU。第一个CPU和第二个CPU可以通过安全的界面进行通信。第一个CPU无法访问第二个CPU中的敏感信息。

4. 发明授权

EP1543526B1 METHOD OF RECOVERING OVERERASED BITS IN A MEMORY DEVICE 有权
标题翻译：一种用于在内存模块RESTORING过度擦除BIT
公开(公告)号：EP1543526B1
公开(公告)日：2008-10-08
申请号：EP03794451.9
申请日：2003-07-30
申请人： ATMEL CORPORATION
发明人： MANEA, Danut, I.
IPC分类号： G11C16/34
CPC分类号： G11C16/344 , G11C16/3404
摘要： A method (Fig. 1) of recovering overerased bits in a memory cell. In the method, a pair of reference currents (I11H, I11L) are internally generated (301) to define a current window corresponding to the erased state ("11") of the memory cell. The first reference current defines the highest current of the current window (12) and the second reference current defines the lowest current of the current window. Then, it is determined (302) which of the memory cells in a memory array are in an overerased state (13) by having an amount of charge on its floating gate that corresponds to a conduction current during a read operation that is greater than the first reference current. Then, the overerased cells are programmed (303; Fig. 8) until the cells are in the erased state.

5. 发明公开

EP1964126A2 ARRAY SOURCE LINE (AVSS) CONTROLLED HIGH VOLTAGE REGULATION FOR PROGRAMMING FLASH OR EE ARRAY 审中-公开
标题翻译：有关阵列源线控制高压控制编程要求的Flash或EE阵列
公开(公告)号：EP1964126A2
公开(公告)日：2008-09-03
申请号：EP06839989.8
申请日：2006-11-21
申请人： ATMEL CORPORATION
发明人： LAMBRACHE, Emil
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , G11C16/0433 , G11C16/12 , G11C16/344 , G11C16/3454 , G11C16/3477 , G11C16/3486
摘要： A method for programming a flash memory array comprises coupling at least one of a current source (410) and a potential source to at least one selected bitline (BL) of a Flash memory array, monitoring a potential VAVSS of an array VSS line (AVSS) by means of a comparator (430), allowing the array VSS line (AVSS) to electrically float until the potential VAVSS is approximately equal to a reference potential Vref , and terminating the programming by de-coupling at least one of the current source (430) and the potential source.

6. 发明公开

EP1952305A2 VECTOR QUANTIZER BASED ON N-DIMENSIONAL SPATIAL DICHOTOMY 审中-公开
标题翻译：矢量量化器基于n维空间二分
公开(公告)号：EP1952305A2
公开(公告)日：2008-08-06
申请号：EP06827562.7
申请日：2006-11-07
申请人： ATMEL CORPORATION
发明人： FIEVET, Sebastien
IPC分类号： G06K9/36
CPC分类号： H03M1/066 , G06K9/6282 , H03M1/0668 , H03M3/464 , H03M3/502 , H03M7/3008
摘要： A method and system for quantizing a vector corresponding to an input signal is described. The vector has a plurality of components corresponding to an N-dimensional space. In one aspect, the method and system include recursively dividing the space into equal spaces having one dimension less than a previous recursion until end spaces are formed. Each end space is two-dimensional. The method and system also include asynchronously comparing the components in each end space to determine a sub-space of a particular end space having a closest match to the vector. In another aspect, the method and system include providing tree(s) including a plurality of nodes and asynchronously traversing the tree(s) to determine a closest match to the vector. The nodes correspond to ANDs of comparisons between the components. Each comparison determines whether a first component is greater than a second component.

7. 发明公开

EP1949420A2 A STRAIN-COMPENSATED METASTABLE COMPOUND BASE HETEROJUNCTION BIPOLAR TRANSISTOR 审中-公开
标题翻译：具有张力的BASE异质结双极型晶体管补偿亚稳态组成
公开(公告)号：EP1949420A2
公开(公告)日：2008-07-30
申请号：EP06839718.1
申请日：2006-11-03
申请人： Atmel Corporation
发明人： ENICKS, Darwin, G. , CHAFFEE, John, T. , CARVER, Damian, A.
IPC分类号： H01L21/20
CPC分类号： H01L29/7842 , H01L29/66242
摘要： A method for pseudomorphic growth and integration of an in-situ doped, strain-compensated metastable compound base (107) into an electronic device (100), such as, for example, a SiGe NPN HBT, by substitutional placement of strain-compensating atomic species. The invention also applies to strained layers in other electronic devices such as strained SiGe, Si in MOS applications, vertical thin film transistors (VTFT), and a variety of other electronic device types. Devices formed from compound semiconductors other than SiGe, such as, for example, GaAs, InP, and AlGaAs are also amenable to beneficial processes described herein.

8. 发明公开

EP1891516A2 SYSTEM AND METHOD FOR POWER SAVING IN PIPELINED MICROPROCESSORS 审中-公开
标题翻译：用于管道式微处理器中的节能的系统和方法
公开(公告)号：EP1891516A2
公开(公告)日：2008-02-27
申请号：EP06760325.8
申请日：2006-05-24
申请人： Atmel Corporation
发明人： RENNO, Erik, K. , STROM, Oyvind
IPC分类号： G06F9/30
CPC分类号： G06F1/3203 , G06F9/30141 , G06F9/3824 , G06F9/3826
摘要： A system and method for preserving power in a microprocessor pipeline (300). The system includes a register file read control unit (305), the read control unit (305) being configured to monitor one or more outputs from a control /decode unit (205) of the pipeline (300) and monitor write addresses from one or more other stages of the pipeline. The system also includes one or more read inhibit units (301, 303) each having an input, an output, and an enable terminal, the output of each of the one or more read inhibit units (301, 303) being coupled to a unique register port of a register file (109) within the pipeline (300). The input of each of the one or more read inhibit units (301, 303) being coupled to the control/decode unit (205), and the enable terminal of each of the one or more read inhibit units (301, 303) being coupled to a unique output of the read control unit (305).
摘要翻译：一种用于在微处理器管线（300）中保存功率的系统和方法。该系统包括寄存器文件读取控制单元（305），读取控制单元（305）被配置为监测来自流水线（300）的控制/解码单元（205）的一个或多个输出并且监视来自一个或多个管道的更多其他阶段。该系统还包括一个或多个读取禁止单元（301,303），每个读取禁止单元具有输入，输出和使能端子，一个或多个读取禁止单元（301,303）中的每一个的输出耦合到唯一的寄存器管道（300）内的寄存器文件（109）的端口。一个或多个读取禁止单元（301,303）中的每一个的输入端耦合到控制/解码单元（205），并且一个或多个读取禁止单元（301,303）中的每一个的使能端被耦合到读取控制单元（305）的唯一输出。

9. 发明公开

EP1889398A2 RANDOMIZED MODULAR POLYNOMIAL REDUCTION METHOD AND HARDWARE THEREFOR 有权转让
标题翻译：对于随机Modularpolynomreduktion和硬件的方法
公开(公告)号：EP1889398A2
公开(公告)日：2008-02-20
申请号：EP06749987.1
申请日：2006-04-12
申请人： ATMEL CORPORATION
发明人： DUPAQUIS, Vincent , DOUGUET, Michel
IPC分类号： H04L9/00
CPC分类号： G06F7/726 , G06F2207/7233
摘要： A cryptographically secure, computer hardware-implemented binary finite-field polynomial modular reduction method estimates (32) and randomizes (36) a polynomial quotient q' (x) used for computation of a polynomial remainder. The randomizing error E (x) injected into the approximate polynomial quotient q (x) is limited to a few bits, e.g. less than half a word. The computed (38) polynomial remainder r' (x) is congruent with but a small random multiple of the residue r (x), which can be found by a final strict binary field reduction by the modulus M (x). In addition to a computational unit (10) and operations sequencer (16), the computing hardware also includes a random or pseudo-random number generator (20) for producing the random polynomial error. The modular reduction method thus resists hardware cryptoanalysis attacks, such as timing and power analysis attacks.

10. 发明公开

EP1889134A2 OUTPUT LEVEL VOLTAGE REGULATION 审中-公开
标题翻译：输出电平电压调节
公开(公告)号：EP1889134A2
公开(公告)日：2008-02-20
申请号：EP06771283.6
申请日：2006-05-25
申请人： Atmel Corporation
发明人： BRACMARD, Gaetan , BOTTARO, Henri
IPC分类号： G05F1/10
CPC分类号： H02M3/157 , G01R31/3004 , G01R31/31703
摘要： A circuit adapting pin output levels to a reference level (60) in which a digital comparator (20) compares an output voltage (40) from an output pin of a device to a reference voltage level (60) . The comparator (20) , relying on the polarity of the comparator output (50, 52) as well as the registered polarity of the comparator output on the previous clock cycle, signals a state machine (22) , which sends a clocked signal to a sense circuit (21) and voltage regulator (30) . The sense circuit (21) may modify a resistance in a switched resistor network (28) , such that the output level is incrementally stepped at clocked intervals towards the reference voltage (60) until the polarity of the error signal reverses. When the output voltage (40) crosses the reference voltage (60) threshold, the comparator (20) flips states and continues to regulate output pin voltage to the reference voltage level (60) .

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式