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1. 发明公开

EP2126922A1 WORD LINE TRANSISTOR STRENGTH CONTROL FOR READ AND WRITE IN SPIN TRANSFER TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY 有权
标题翻译： STEUERUNG DERWORTZEILENTRANSISTORSTÄRKEZUM LESEN UND SCHREIBEN IN EINEM MAGNETORESISTIVEN STT-RAM
公开(公告)号：EP2126922A1
公开(公告)日：2009-12-02
申请号：EP08731574.3
申请日：2008-03-06
申请人： QUALCOMM INCORPORATED
发明人： YOON, Sei Seung , KANG, Seung H. , SANI, Mehdi Hamidi
IPC分类号： G11C11/16
CPC分类号： G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： Systems, circuits and methods for controlling word line voltage at a word line transistor in Spin Transfer Torque Magnetoresistive Random Access Memory (STT- MRAM) are disclosed. A first voltage can be supplied to the word line transistor for write operations. A second voltage, which is less than the first voltage, can be supplied to the word line transistor during read operations.
摘要翻译：公开了用于控制旋转传递扭矩磁阻随机存取存储器（STT-MRAM）中的字线晶体管的字线电压的系统，电路和方法。可以向字线晶体管提供第一电压用于写入操作。在读取操作期间，可以将小于第一电压的第二电压提供给字线晶体管。

2. 发明公开

EP3193336A1 REDUCING LEAKAGE CURRENT IN A MEMORY DEVICE 审中-公开
标题翻译：降低存储设备中的泄漏电流
公开(公告)号：EP3193336A1
公开(公告)日：2017-07-19
申请号：EP17156313.3
申请日：2010-02-02
申请人： QUALCOMM Incorporated
发明人： CHEN, Nan , SANI, Mehdi Hamidi , CHABA, Ritu
IPC分类号： G11C17/18 , G11C5/14 , G11C7/12
CPC分类号： G11C17/18 , G11C5/14 , G11C5/147 , G11C7/12
摘要： Memory devices and methods of reducing leakage current therein are disclosed. The memory device includes a memory core array including a plurality of bitlines, and peripheral logic configured to interface with the memory core array. The memory device further includes a footswitch configured to isolate the peripheral logic from a ground voltage, and a headswitch configured to isolate a precharge current path from the plurality of bit lines of the memory core array. Leakage current within the memory device may be reduced via the isolation provided by the footswitch and the headswitch.
摘要翻译：公开了减少其中泄漏电流的存储器件和方法。存储器装置包括包含多个位线的存储器核心阵列，以及经配置以与存储器核心阵列介接的外围逻辑。所述存储器装置进一步包含经配置以将所述外围逻辑与接地电压隔离的脚踏开关以及经配置以将预充电电流路径与所述存储器核心阵列的所述多个位线隔离的头部开关。存储装置内的泄漏电流可通过脚踏开关和头部开关提供的隔离而降低。

3. 发明授权

EP2380175B1 BALANCING A SIGNAL MARGIN OF A RESISTANCE BASED MEMORY CIRCUIT 有权
标题翻译：克服了信号预留存储器电路电阻的基层
公开(公告)号：EP2380175B1
公开(公告)日：2016-03-30
申请号：EP09802075.3
申请日：2009-12-18
申请人： QUALCOMM Incorporated
发明人： JUNG, Seong-Ook , KIM, Jisu , SONG, Jee-Hwan , KANG, Seung H. , YOON, Sei Seung , SANI, Mehdi Hamidi
IPC分类号： G11C11/16
CPC分类号： G11C7/14 , G11C7/12 , G11C11/1673

4. 发明授权

EP2353164B1 WORD LINE VOLTAGE CONTROL IN STT-MRAM 有权
标题翻译：字线电压控制在STT-MRAM
公开(公告)号：EP2353164B1
公开(公告)日：2014-12-17
申请号：EP09748663.3
申请日：2009-11-04
申请人： QUALCOMM Incorporated
发明人： YOON, Sei Seung , SANI, Mehdi Hamidi , KANG, Seung H.
IPC分类号： G11C11/16 , G11C8/08
CPC分类号： G11C8/08 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675

5. 发明公开

EP1510006A2 NON-VOLATILE MULTI-THRESHOLD CMOS LATCH WITH LEAKAGE CONTROL 有权
标题翻译：非易失性CMOS闩多个阈值和泄漏流量控制
公开(公告)号：EP1510006A2
公开(公告)日：2005-03-02
申请号：EP03741807.6
申请日：2003-05-23
申请人： Qualcomm, Incorporated
发明人： SANI, Mehdi Hamidi , UVIEGHARA, Gregory A.
IPC分类号： H03K3/356
CPC分类号： H01L27/092 , H03K3/0375 , H03K3/356121
摘要： An integrated circuit including a Multi-Threshold CMOS (MTCMOS) latch combining low voltage threshold CMOS circuits with high voltage threshold CMOS circuits. The low voltage threshold circuits including a majority of the circuits in the signal path of the latch to ensure high performance of the latch. The latch further including high voltage circuits to eliminate leakage paths from the low voltage threshold circuits when the latch is in a sleep mode. A single-phase latch and a two-phase latch are provided. Each of the latches is implemented with master and slave registers. Data is held in either the master register or the slave register depending on the phase or phases of the clock signals. A multiplexer may alternatively be implemented prior to the master latch for controlling an input signal path during sleep and active modes of the latch and for providing a second input signal path for test.

6. 发明授权

EP2130206B1 READ DISTURB REDUCTION CIRCUIT FOR SPIN TRANSFER TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY 有权
标题翻译：诵读困难消除器MAGNETORESISITVEN STT-RAM
公开(公告)号：EP2130206B1
公开(公告)日：2014-07-09
申请号：EP08743709.1
申请日：2008-03-06
申请人： QUALCOMM Incorporated
发明人： YOON, Sei Seung , KANG, Seung H. , SANI, Mehdi Hamidi
IPC分类号： G11C7/06 , G11C11/16
CPC分类号： G11C7/02 , G11C7/062 , G11C7/067 , G11C7/12 , G11C11/1673

7. 发明公开

EP2353164A1 WORD LINE VOLTAGE CONTROL IN STT-MRAM 有权
标题翻译： STT-MRAM中的WORTLEITUNGSSPANNUNGSREGELUNG
公开(公告)号：EP2353164A1
公开(公告)日：2011-08-10
申请号：EP09748663.3
申请日：2009-11-04
申请人： QUALCOMM Incorporated
发明人： YOON, Sei Seung , SANI, Mehdi Hamidi , KANG, Seung H.
IPC分类号： G11C11/16
CPC分类号： G11C8/08 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： Systems, circuits and methods for controlling the word line voltage applied to word line transistors (410) in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnetic tunnel junction (MTJ, 405) and a word line transistor. The bit cell is coupled to a bit line (420) and a source line (440). A word line driver (432) is coupled to a gate of the word line transistor. The word line driver is configured to provide a word line voltage greater than a supply voltage below "a transition voltage of the supply voltage and to provide a voltage less than the supply voltage for supply voltages above the transition voltage.
摘要翻译：公开了用于控制施加到自旋转移磁阻随机存取存储器（STT-MRAM）中的字线晶体管的字线电压的系统，电路和方法。一个实施例涉及包括具有磁性隧道结（MTJ）的位单元和字线晶体管的STT-MRAM。位单元耦合到位线和源极线。字线驱动器耦合到字线晶体管的栅极。字线驱动器被配置为提供大于低于电源电压的转换电压的电源电压的字线电压，并且为高于转换电压的电源电压提供小于电源电压的电压。

8. 发明授权

EP1510006B1 NON-VOLATILE MULTI-THRESHOLD CMOS LATCH WITH LEAKAGE CONTROL 有权
标题翻译：非易失性CMOS闩多个阈值和泄漏流量控制
公开(公告)号：EP1510006B1
公开(公告)日：2008-10-22
申请号：EP03741807.6
申请日：2003-05-23
申请人： Qualcomm, Incorporated
发明人： SANI, Mehdi Hamidi , UVIEGHARA, Gregory A.
IPC分类号： H03K3/356
CPC分类号： H01L27/092 , H03K3/0375 , H03K3/356121
摘要： An integrated circuit including a Multi-Threshold CMOS (MTCMOS) latch combining low voltage threshold CMOS circuits with high voltage threshold CMOS circuits. The low voltage threshold circuits including a majority of the circuits in the signal path of the latch to ensure high performance of the latch. The latch further including high voltage circuits to eliminate leakage paths from the low voltage threshold circuits when the latch is in a sleep mode. A single-phase latch and a two-phase latch are provided. Each of the latches is implemented with master and slave registers. Data is held in either the master register or the slave register depending on the phase or phases of the clock signals. A multiplexer may alternatively be implemented prior to the master latch for controlling an input signal path during sleep and active modes of the latch and for providing a second input signal path for test.

9. 发明公开

EP1861973A1 CURRENT MODE INTERFACE FOR OFF-CHIP HIGH SPEED COMMUNICATION 审中-公开
标题翻译：电动接口，OFF-CHIP高速通信
公开(公告)号：EP1861973A1
公开(公告)日：2007-12-05
申请号：EP06739775.2
申请日：2006-03-23
申请人： QUALCOMM INCORPORATED
发明人： DIXIT, Abhay , SANI, Mehdi Hamidi , MOHAN, Vivek
IPC分类号： H04L25/02 , H04L25/08 , H03K19/0175
CPC分类号： H03K19/018514 , H01L2224/49175 , H01L2924/3011 , H01L2924/30111 , H04L25/0272 , H04L25/0278 , H04L25/0282 , H04L25/0294 , H01L2924/00
摘要： A transceiver interface for data transfer between two integrated circuits (ICs or 'chips') utilizes a current mode technique rather than conventional voltage mode differential signaling techniques. A current pulse is injected into one of two transmission wires based on a signal value to be transmitted (e.g., logic '0' or '1') by a driver on a transmitting chip. The current pulse is received as a differential current signal at a receive block in a receiving chip. The differential current signal is converted to a low swing differential voltage signal by current comparators. The differential voltage signal may be detected by an op-amp receiver which outputs the appropriate signal value.

10. 发明授权

EP2332142B1 MEMORY DEVICE FOR RESISTANCE-BASED MEMORY APPLICATIONS 有权
标题翻译：存储设备电阻式存储器应用
公开(公告)号：EP2332142B1
公开(公告)日：2013-07-10
申请号：EP09792136.5
申请日：2009-09-01
申请人： QUALCOMM Incorporated
发明人： DAVIERWALLA, Anosh B. , ZHONG, Cheng , PARK, Dongkyu , ABU-RAHMA, Mohamed Hassan , SANI, Mehdi Hamidi , YOON, Sei Seung
IPC分类号： G11C7/06 , G11C7/10 , G11C7/12 , G11C7/14 , G11C11/16
CPC分类号： G11C11/1673

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