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1. 发明公开

EP4348648A1 SELF REFRESH OF MEMORY CELL 审中-实审
公开(公告)号：EP4348648A1
公开(公告)日：2024-04-10
申请号：EP22817001.5
申请日：2022-05-13
申请人： MICRON TECHNOLOGY, INC.
发明人： CARMAN, Eric, S.
IPC分类号： G11C11/406 , G11C11/4094 , G11C11/408 , G11C11/4074

2. 发明授权

EP2309513B1 BIAS SENSING IN DRAM SENSE AMPLIFIERS 有权
公开(公告)号：EP2309513B1
公开(公告)日：2019-07-10
申请号：EP10185622.7
申请日：2003-08-26
申请人： Micron Technology, Inc.
发明人： McElroy, David J. , Casper, Stephen L.
IPC分类号： G11C7/12 , G11C11/4094 , G11C7/06

3. 发明公开

EP3149735A4 POWER REDUCTION IN THYRISTOR RANDOM ACCESS MEMORY 审中-公开
公开(公告)号：EP3149735A4
公开(公告)日：2018-06-13
申请号：EP15844668
申请日：2015-09-25
申请人： KILOPASS TECH INC
发明人： LUAN HARRY , BATEMAN BRUCE , AXELRAD VALERY , CHENG CHARLIE
IPC分类号： G11C11/39 , G06F11/10 , G11C11/402 , G11C11/406 , G11C11/4067 , G11C11/408 , G11C11/4094 , H01L27/102 , H01L29/66
CPC分类号： H01L27/1027 , G06F11/1048 , G11C11/39 , G11C11/4026 , G11C11/406 , G11C11/4067 , G11C11/408 , G11C11/4094 , H01L21/76 , H01L21/76224 , H01L27/1023 , H01L29/66121 , H01L29/87
摘要： A volatile memory array using vertical thyristors is disclosed together with methods of reducing power consumption in such arrays.

4. 发明公开

EP2764515A1 REDUCED NOISE DRAM SENSING 审中-公开
标题翻译：噪声降低的DRAM检测
公开(公告)号：EP2764515A1
公开(公告)日：2014-08-13
申请号：EP12838980.6
申请日：2012-10-03
申请人： Conversant Intellectual Property Management Inc.
发明人： CHOI, Byoung Jin
IPC分类号： G11C11/4094 , G11C11/4091 , G11C11/4097
CPC分类号： G11C7/12 , G11C7/02 , G11C11/4087 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002
摘要： A dynamic random access memory device is described. A first array has a first plurality of bitlines, each coupled to a column of memory cells. A second has a second plurality of bitlines, each coupled to a column of memory cells. Sense amplifiers are selectively connectable in an open bitline configuration to at least one bitline of the first plurality of bitlines and at least one complementary bitline of the second plurality of bitlines. A voltage supply having a voltage VBL corresponding to a bitline precharge voltage is selectively connectable to each bitline. Logic selectively connects each bitline and the complementary bitline to one of a sense amplifier and the voltage supply during a read operation. Each bitline connected to the sense amplifier is adjacent to a bitline concurrently connected to the voltage supply. A method is also described.

5. 发明公开

EP2518727A1 Differential sense amplifier without dedicated precharge transistors 审中-公开
标题翻译：差异分析师哇哇哇。。。。。。。。。
公开(公告)号：EP2518727A1
公开(公告)日：2012-10-31
申请号：EP12162172.6
申请日：2012-03-29
申请人： Soitec
发明人： Ferrant Richard , Thewes Roland
IPC分类号： G11C7/06 , G11C7/12 , G11C11/4091 , G11C11/4094
CPC分类号： G11C7/065 , G11C7/12 , G11C11/4091 , G11C11/4094
摘要： The invention A differential sense amplifier for sensing data stored in a plurality of memory cells (C) of a memory cell array, including:
- a first CMOS inverter having an output connected to a first bit line (BL) and an input connected to a second bit line (/BL) complementary to the first bit line,
- a second CMOS inverter having an output connected to the second bit line (/BL) and an input connected to the first bit line (BL),
each CMOS inverter comprising a pull-up transistor (M21, M22) and a pull-down transistor (M31, M32), said sense amplifier having a pair of precharge transistors arranged to be respectively coupled to said first and second bit lines (BL, /BL), so as to precharge said first and second bit lines (BL, /BL) to a precharge voltage, wherein said precharge transistors are constituted by the pull-up transistors (M21, M22) or by the pull-down transistors (M31, M32).
摘要翻译：本发明一种用于感测存储在存储单元阵列的多个存储单元（C）中的数据的差分读出放大器，包括： - 具有连接到第一位线（BL）的输出的第一CMOS反相器和连接到与第一位线互补的第二位线（/ BL）， - 具有连接到第二位线（/ BL）的输出和连接到第一位线（BL）的输入的第二CMOS反相器，每个CMOS反相器包括上拉晶体管（M21，M22）和下拉晶体管（M31，M32），所述读出放大器具有一对分别耦合到所述第一和第二位线（BL，/ BL）的预充电晶体管，因此将所述第一和第二位线（BL，/ BL）预充电到预充电电压，其中所述预充电晶体管由上拉晶体管（M21，M22）或下拉晶体管（M31，M32）构成。

6. 发明公开

EP1619690A3 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：EP1619690A3
公开(公告)日：2007-10-17
申请号：EP05021546.6
申请日：2001-02-27
申请人： FUJITSU LIMITED
发明人： Fujioka, Shinya , Ikeda, Hitoshi , Matsumiya, Masato
IPC分类号： G11C11/404 , G11C11/4091 , G11C11/4094 , G11C7/06 , G11C11/408 , G11C11/4076 , G11C7/22
CPC分类号： G11C7/065 , G11C7/12 , G11C7/22 , G11C11/4076 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C2207/002 , G11C2207/005 , G11C2211/4013
摘要： A semiconductor memory device comprising: bit lines (BL, /BL) in pairs; a sense amplifier (400-0) that is connected to each pair of the bit lines (BL, /BL); a first memory cell (MC00) that is connected to one bit line (BL) of each pair of the bit lines (BL, /BL); a second memory cell (MC10) that is connected to the other bit line (/BL) of each pair of the bit lines (BL, /BL), and stores inverted data of data stored in the first memory cell (MC00); a word line (WL) connected to every other pair of the bit lines (BL, /BL); an open-close column gate (40, 41) that connects the bit lines (BL, /BL) to a data bus (DB); and a control circuit (15, CL) that controls the column gate (40, 41) to open before the sense amplifier (400-0) is activated in a data write operation. The semiconductor memory device of the present invention is also characterized by including a control circuit (11) that controls the sense amplifier (400-0, 400-1) to start a pull-down operation after starting a pull-up operation. Such a device has an operation control method and a circuit structure that allows a higher process rate, less power consumption, and a smaller chip area.
摘要翻译：一种半导体存储器件，包括：成对的位线（BL，/ BL）连接到每对位线（BL，/ BL）的读出放大器（400-0）; 与每对位线（BL，/ BL）中的一条位线（BL）连接的第一存储单元（MC00）第二存储单元（MC10），其与各位线（BL，/ BL）的另一位线（/ BL）连接，并存储第一存储单元（MC00）中存储的数据的反转数据; 连接到每隔一对位线（BL，/ BL）的字线（WL）; 将位线（BL，/ BL）连接到数据总线（DB）的开闭列门（40,41）; 以及控制电路（15，CL），其在数据写入操作中激活读出放大器（400-0）之前控制列门（40,41）打开。本发明的半导体存储器件的特征还在于包括在开始上拉操作之后控制读出放大器（400-0,400-1）开始下拉操作的控制电路（11）。这种设备具有允许更高处理速率，更少功耗和更小芯片面积的操作控制方法和电路结构。

7. 发明授权

EP1433179B1 SYSTEM AND METHOD FOR EARLY WRITE TO MEMORY BY HOLDING BITLINE AT FIXED POTENTIAL 有权
标题翻译：系统和方法的早期著述IN MEMORY通过保持对公司潜在位线
公开(公告)号：EP1433179B1
公开(公告)日：2006-05-24
申请号：EP01995491.6
申请日：2001-12-10
申请人： International Business Machines Corporation
发明人： BARTH, John, E., Jr. , PILO, Harold
IPC分类号： G11C7/00 , G11C7/12 , G11C11/4094 , G11C11/4091
CPC分类号： G11C7/22 , G11C7/12 , G11C2207/104
摘要： A system and method is disclosed for writing early within a memory cycle by holding only one of a true bitline (BTO) and a reference bitline (BC0) at a fixed potential, e.g. ground, when the sense amplifier (51) is set. The sense amplifier (51) amplifies a small voltage difference between the true bitline (BT0) and the reference bitline (BC0) to predetermined high and low voltage logic levels to write a datum to the memory cell. In this way, writing can complete in about the same time as reading, without risking corruption of data on adjacent bitlines in the memory. The bitlines are precharged to a fixed potential in a conduction path through the bitswitches (T1), rather than using local precharge devices at the sense amplifier (51). To write, bitswitches (T1) and writepath transistors (T3) apply the fixed potential to one of the true bitline (BT0) and the reference bitline (BC0). Bitswitches (T1) on such other memory cells not currently being written isolate the bitline coupled to those memory cells when setting the sense amplifiers, such that the stored contents of such memory cells not being written are refreshed (written back) at the time that the selected memory cell is written.

8. 发明公开

EP1349174A3 Memory embedded logic integrated circuit mounting memory circuits having different performances on the same chip 审中-公开
标题翻译：与具有两个Halbleiterspeicheranordnungenen用相同的块上不同功能的内置逻辑电路的半导体存储器件
公开(公告)号：EP1349174A3
公开(公告)日：2004-06-16
申请号：EP02011553.1
申请日：2002-05-24
申请人： Kabushiki Kaisha Toshiba
发明人： Kaneko, Tetsuya, Intellectual Property Division
IPC分类号： G11C11/401 , G11C11/4074 , G11C11/408 , G11C7/12 , G11C11/4094 , G11C11/4097 , G11C7/18 , H01L21/8242
CPC分类号： G11C7/12 , G11C11/401 , G11C11/4074 , G11C11/4085 , G11C11/4094 , G11C2207/104
摘要： A semiconductor integrated circuit includes a first DRAM circuit (13-1) having a first memory cell array having a plurality of memory cells each including a first MOS transistor, and a first potential generating circuit which generates at least one potential used to operate the plurality of memory cells in the first memory cell array, the first DRAM circuit being formed in a semiconductor chip (11), and a second DRAM circuit (13-2) having a second memory cell array having a plurality of memory cells each including a second MOS transistor different in characteristic from the first MOS transistor, and a second potential generating circuit which generates at least one potential used to operate the plurality of memory cells in the second memory cell array, the second DRAM circuit being formed in the semiconductor chip.

9. 发明授权

EP1168359B1 Procédé de commande d'un accès en lecture d'une mémoire vive dynamique et mémoire correspondante. 有权
标题翻译： Vefahren Steurung对于读取访问动态内存并
公开(公告)号：EP1168359B1
公开(公告)日：2004-02-18
申请号：EP01401558.0
申请日：2001-06-14
申请人： STMicroelectronics SA
发明人： Ferrant, Richard
IPC分类号： G11C11/4094
CPC分类号： G11C11/4094

10. 发明公开

EP0732701A3 Bit-line precharge current limiter for CMOS dynamic memories 失效
标题翻译： Bitleitungsvorladungsstrombegrenzer for CMOS dynamische Speicher
公开(公告)号：EP0732701A3
公开(公告)日：1998-11-25
申请号：EP96480016
申请日：1996-02-06
申请人： IBM
发明人： KIRIHATA TOSHIAKI , WATANABE YOHJI , FUJII SHUSO
IPC分类号： G11C11/409 , G11C11/401 , G11C11/4094 , G11C29/04
CPC分类号： G11C11/4094
摘要： A fault-tolerant DRAM design minimizes current flow in the event of a cross-fail. A bit-line precharge current limiter is provided for the bit-line precharge equalizer circuit. The bit-line precharge current limiter is both simple and effective, requiring very little silicon area to implement. The current limiter provides self current-limiting for defective bit-lines, without the necessity for a reference cell.
摘要翻译：容错DRAM设计可以在发生交叉故障时最大限度地减少电流。为位线预充电均衡器电路提供位线预充电电流限制器。位线预充电电流限制器既简单又有效，需要很少的硅面积来实现。电流限制器为有缺陷的位线提供自限流，而不需要参考单元。

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