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91. 发明公开

EP0657893A3 High-density read-only data storage 失效
标题翻译：高密度只读数据存储
公开(公告)号：EP0657893A3
公开(公告)日：1995-11-22
申请号：EP94308848.4
申请日：1994-11-30
申请人： AT&T Corp.
发明人： Shoji, Masakazu
IPC分类号： G11C17/12 , H01L27/112 , H01L21/8246
CPC分类号： H01L27/11273 , G11C17/12 , H01L27/112
摘要： A read-only memory ("ROM") utilizing junction field-effect transistors ("JFETs") each having a conductive channel (107,108) orthogonally oriented with respect to the surface of the semiconductor material (101,102,104) composing the JFET. A fixed-position ion beam is employed to create this narrow gate channel, which extends between the JFET's source (104) and drain contact (e.g. 105). Employing such JFETs as basic memory sites within a semiconductor ROM circuit allows for an architecture that conforms to a minimum lattice structure layout. In addition, the resulting ROM offers high speed access of data. Although JFETs have not been utilized as the transistor of choice within ROMs because of their seemingly inferior performance when compared to MOSFETs, the invention provides a novel architecture which significantly enhances the practicality of the JFET as a memory device.
摘要翻译：一种利用结型场效应晶体管（“JFET”）的只读存储器（“ROM”），每个晶体管具有相对于组成JFET的半导体材料（101,102,104）的表面正交定向的导电沟道（107,108）。使用固定位置的离子束来形成该狭窄的栅极沟道，其在JFET的源极（104）和漏极接触（例如105）之间延伸。在半导体ROM电路内采用这种JFET作为基本存储器位置允许符合最小栅格结构布局的架构。另外，由此产生的ROM提供高速访问数据。尽管JFET没有被用作ROM内选择的晶体管，因为与MOSFET相比，它们的性能似乎较差，本发明提供了一种新颖的架构，其显着增强了JFET作为存储器件的实用性。

92. 发明授权

EP0399362B1 A sense amplifier circuit 失效
标题翻译：读出放大器电路。
公开(公告)号：EP0399362B1
公开(公告)日：1995-02-15
申请号：EP90109264.3
申请日：1990-05-16
申请人： FUJITSU LIMITED
发明人： Kasa, Yasushi
IPC分类号： G11C7/00 , G11C7/06 , G11C16/06 , G11C17/12
CPC分类号： G11C7/067 , G11C7/12 , G11C16/26 , G11C17/12

93. 发明公开

EP0601207A1 DATA READ METHOD AND READ ONLY MEMORY CIRCUIT 失效
标题翻译：数据读取方法和只读存储器电路
公开(公告)号：EP0601207A1
公开(公告)日：1994-06-15
申请号：EP93913597.6
申请日：1993-06-28
申请人： Oki Electric Industry Company, Limited
发明人： HARADA, Teruhiro Oki Electronic Industry Co. Ltd.
IPC分类号： G11C16/06 , G11C17/12
CPC分类号： G11C17/126 , G11C16/26
摘要： A given column line and a bit line adjacent to it are selected from a plurality of string lines (102-1 to 102-3) and bit lines (101-1 to 101-2) by the string selection signals (Y₁ to Y₃); and a given row line is selected from a plurality of row lines (103-1 to 103-n) by the row selection signals (X₀ to X n ). The data stored in the memory cells (104-01 to 104-n4) which are connected to the selected column line and row line are read out on the selected bit line. The selected column line is made to be at a first potential level (the potential level supplied from a constant-voltage circuit (160)). Substantially at the same time, the selected bit line is made to be at a second potential level (the potential level provided by a sense amplifying circuit (150)) which is lower than the first potential. The column lines which are not selected are made to be at a third potential level (the ground potential level or the potential level provided by a potential supply circuit (190)) which is lower than the second potential level. Then, the data are read out. Therefore, it is possible to read the data at a high speed, and further, to materialize a low power consumption because no reactive current flows.
摘要翻译：通过串选择信号（Y 1至Y 3）从多个串行（102-1至102-3）和位线（101-1至101-2）中选择给定的列线和与其相邻的位线， ; 并通过行选择信号（X 0至X n）从多个行线（103-1至103-n）中选择给定的行线。存储在连接到所选列线和行线的存储单元（104-01到104-n4）中的数据在所选位线上被读出。所选择的列线被制成处于第一电位电平（从恒压电路（160）提供的电位电平）。基本上同时，所选位线被设置为低于第一电位的第二电位电平（由读出放大电路（150）提供的电位电平）。未被选择的列线被制成处于比第二电位电平低的第三电位电平（地电位电平或由电位供给电路（190）提供的电位电平）。然后，数据被读出。因此，可以高速读取数据，并且进一步实现低功耗，因为没有无功电流流动。

94. 发明公开

EP0499460A3 Semiconductor memory device 失效
公开(公告)号：EP0499460A3
公开(公告)日：1993-10-06
申请号：EP92301171.2
申请日：1992-02-13
申请人： SHARP KABUSHIKI KAISHA
发明人： Hotta, Yashuhiro
IPC分类号： G11C7/06 , G11C17/12 , G11C11/419 , G11C16/06
CPC分类号： G11C16/26 , G11C7/06 , G11C11/419 , G11C17/12
摘要： In a semiconductor memory device, two sense amplifiers are provided on one output signal line for reading data stored in a memory cell. The sense amplifiers are connected in parallel to each other. A control signal generation circuit generates a control signal so that one of the sense amplifiers which has a greater drive capability is activated during a predetermined time period after an address from which data is to be read out is changed, and that the sense amplifier having a smaller drive capability is activated during a time period other than the predetermined time period.

95. 发明公开

EP0467607A3 Semiconductor memory device 失效
公开(公告)号：EP0467607A3
公开(公告)日：1993-04-07
申请号：EP91306365.7
申请日：1991-07-15
申请人： NEC CORPORATION
发明人： Kohno, Takaki, c/o NEC CORPORATION
IPC分类号： G11C17/12
CPC分类号： G11C17/123
摘要： Electric field stress applied to memory cells (107) is relieved in a semiconductor memory device. For this purpose, an X-decoder circuit (104) applies a low level signal to a selected memory cell in a selected memory cell block of a selected memory cell matrix, and a high level signal to non-selected memory cells in the selected memory cell block, while the X-decoder circuit applies the low level signal to memory cells of non-selected memory cell blocks of the selected memory cell matrix and memory cells of non-selected memory cell matrices.

96. 发明公开

EP0530713A2 Nonvolatile memory circuit 失效
标题翻译： NichtflüchtigeSpeicherschaltung。
公开(公告)号：EP0530713A2
公开(公告)日：1993-03-10
申请号：EP92114763.3
申请日：1992-08-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Matsumoto, Osamu, c/o Intell. Property Div. , Miki, Kazuhiko, c/o Intell. Property Div.
IPC分类号： G11C16/06 , G11C17/12
CPC分类号： G11C17/12 , G11C16/28 , G11C16/30
摘要： The present invention relates to a precharge/discharge nonvolatile memory circuit for detecting signals output from two bit lines on read-cell and dummy cell sides using a flip-flop circuit, comprising a first row decoder (11) on the read-cell side, a second row decoder (11) on the dummy-cell side, a first column decoder (14-1) on the read-cell side, a second column decoder (14-2) on the dummy-cell side, a read cell (12) selected by the first row decoder (11) and the first column decoder (14-1), a dummy cell (15) selected by the second row decoder (11) and the second column decoder (14-2), first and second precharge transistors (P1, P2) for performing a precharge operation, first and second discharge transistors (D1, D2) for performing a discharge operation, the flip-flop circuit (18), a discharge control circuit (21) for generating a discharge signal, and a precharge control circuit (22) for generating a precharge signal after the discharge signal is generated from the discharge control circuit (21).
摘要翻译：本发明涉及一种预充电/放电非易失性存储电路，用于使用触发器电路来检测从读取单元和虚设单元侧的两个位线输出的信号，该触发器电路包括读单元侧的第一行解码器（11）虚拟单元侧的第二行解码器（11），读取单元侧的第一列解码器（14-1），虚拟单元侧的第二列解码器（14-2），读取单元由第一行解码器（11）和第一列解码器（14-1）选择的第二行解码器（11）和第二列解码器（14-2）选择的虚拟单元（15），第一和第用于执行预充电操作的第二预充电晶体管（P1，P2），用于进行放电操作的第一和第二放电晶体管（D1，D2），触发器电路（18），用于产生放电的放电控制电路信号，以及用于在从放电控制产生放电信号之后产生预充电信号的预充电控制电路（22）（21）。

97. 发明公开

EP0508588A2 Semiconductor read only memory 失效
标题翻译： Halbleiterfestwertspeicher。
公开(公告)号：EP0508588A2
公开(公告)日：1992-10-14
申请号：EP92301850.1
申请日：1992-03-04
申请人： SHARP KABUSHIKI KAISHA
发明人： Hotta, Yasuhiro
IPC分类号： G11C17/12
CPC分类号： G11C17/126 , G11C17/12
摘要： A semiconductor read only memory with hierarchical bit lines in which a resistance against a discharge current is constant irrespective of the position of a memory cell from which information is to be read is disclosed. A bank selecting MOSFET is connected to one end portion of a sub-bit line. Another bank selecting MOSFET is connected to the other end portion of the adjacent sub-bit line. Bank selecting MOSFETs are connected in the same alternate manner as described above. Therefore, since the resistance on bit lines against the read-out current is constant, a larger read-out current can be used especially when diffusion bit lines are used, whereby the semiconductor read only memory of the invention can achieve a high-speed read operation.
摘要翻译：公开了一种具有分级位线的半导体只读存储器，其中对于放电电流的电阻是恒定的，而与要读取信息的存储器单元的位置无关。存储体选择MOSFET连接到子位线的一个端部。另一组选择MOSFET连接到相邻子位线的另一端部分。银行选择MOSFET以与上述相同的交替方式连接。因此，由于针对读出电流的位线上的电阻是恒定的，所以特别是当使用扩散位线时可以使用更大的读出电流，由此本发明的半导体只读存储器可以实现高速读取操作。

98. 发明公开

EP0499460A2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0499460A2
公开(公告)日：1992-08-19
申请号：EP92301171.2
申请日：1992-02-13
申请人： SHARP KABUSHIKI KAISHA
发明人： Hotta, Yashuhiro
IPC分类号： G11C7/06 , G11C17/12 , G11C11/419 , G11C16/06
CPC分类号： G11C16/26 , G11C7/06 , G11C11/419 , G11C17/12
摘要： In a semiconductor memory device, two sense amplifiers are provided on one output signal line for reading data stored in a memory cell. The sense amplifiers are connected in parallel to each other. A control signal generation circuit generates a control signal so that one of the sense amplifiers which has a greater drive capability is activated during a predetermined time period after an address from which data is to be read out is changed, and that the sense amplifier having a smaller drive capability is activated during a time period other than the predetermined time period.
摘要翻译：在半导体存储装置中，在一个输出信号线上提供两个读出放大器，用于读取存储在存储单元中的数据。读出放大器彼此并联连接。控制信号生成电路生成控制信号，使得在读出数据的地址改变后的预定时间段内激活具有较大驱动能力的一个读出放大器，并且使读出放大器具有在预定时间段以外的时间段内激活较小的驱动能力。

99. 发明公开

EP0342880A3 Semiconductor non-volatile memory device 失效
标题翻译：半导体非易失性存储器件
公开(公告)号：EP0342880A3
公开(公告)日：1992-05-27
申请号：EP89304848.8
申请日：1989-05-12
申请人： Matsushita Electronics Corporation
发明人： Kojima, Makoto , Takata, Takashi
IPC分类号： G11C16/04 , G11C16/06 , G11C17/12
CPC分类号： G11C16/10 , G11C16/0466 , G11C16/14 , G11C16/26 , G11C17/123 , H01L29/792
摘要： This invention relates to a semiconductor non-volatile memory device, in which plural data storage parts are connected in series between the source region and drain region. In such constitution, when integrating the semiconductors, the relative area occupied by the selection gate, separation gate, source region and drain region of the area of the data storage parts may be drastically reduced, and the degree of integration of semiconductor non-volatile memory device can be dramatically enhanced. This invention also comprises means for setting the semiconductor substrate in depletion state by sequentially varying the gate potential of the plural data storage parts and transferring the electric charges sequentially. By this means for transferring electric charges, data write errors may be securely prevented.

100. 发明公开

EP0453206A2 Memory device 失效
标题翻译： Speicheranordnung。
公开(公告)号：EP0453206A2
公开(公告)日：1991-10-23
申请号：EP91303294.2
申请日：1991-04-15
申请人： NEC CORPORATION
发明人： Hikichi, Hiroshi, c/o NEC Corporation
IPC分类号： G11C5/14 , G11C7/00 , G11C17/12
CPC分类号： G11C5/147 , G11C7/22 , G11C17/12 , G11C2207/063
摘要： A memory device of the invention has memory cells (Q101,Q102) each of which is addressed according to a timing signal (øa), current sense amplifiers (1) each of which determines whether a current flows in the addressed memory cell or not and reads out data stored in such memory cell, a circuit (FD1,DL,AD1; DL,AD2,FF3) which generates a control signal to become active at a timing when the memory cell is addressed and to become inactive after read-out of the stored data is completed, and a circuit (I4,I2,NR1; I4,FF2,NR1) which cuts-off based on the control signal a path for a steady-state current flowing in the current sense amplifier.
摘要翻译：本发明的存储器件具有存储单元（Q101，Q102），每个存储单元根据定时信号（oa）被寻址，电流检测放大器（1）确定电流是否流过所寻址的存储单元，读出存储在这样的存储单元中的数据，电路（FD1，DL，AD1; DL，AD2，FF3），其在存储单元被寻址的定时产生控制信号以变为有效，并且在读出存储的数据完成，并且基于控制信号切断在电流感测放大器中流动的稳态电流的路径的电路（I4，I2，NR1; I4，FF2，NR1）。

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