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1. 发明授权

EP0880144B1 Read only memory 失效
标题翻译： Festwertspeicher
公开(公告)号：EP0880144B1
公开(公告)日：2005-02-23
申请号：EP98304119.5
申请日：1998-05-26
申请人： Samsung Electronics Co., Ltd.
发明人： Choi, Byung-Sun
IPC分类号： G11C17/12 , G11C7/00
CPC分类号： G11C17/126 , G11C7/18

2. 发明公开

EP1047079A2 Semiconductor memory device generating accurate internal reference voltage 有权
标题翻译：与精确的内部基准电压产生的半导体存储器件
公开(公告)号：EP1047079A2
公开(公告)日：2000-10-25
申请号：EP00104670.5
申请日：2000-03-03
申请人： Oki Electric Industry Co., Ltd.
发明人： Miyamoto, Kenichi, c/o OKI Micro Design Co., Ltd.
IPC分类号： G11C17/12 , G11C7/14
CPC分类号： G11C17/126 , G11C7/14 , G11C17/123
摘要： A semiconductor memory device has a memory cell array that outputs cell current to data sensing amplifiers and reference current to reference amplifiers. The reference amplifiers convert the reference current to a reference voltage. The data sensing amplifiers use the reference voltage to convert the cell current to a data voltage signal. According to a first aspect of the invention, reference current is supplied to a reference amplifier from two parallel data paths, each having approximately equal numbers of transistors of two types, one type of which is always switched on, the other type switching on and off. According to a second aspect of the invention, each data sensing amplifier, and the reference amplifier to which it is connected, receive currents from parts of the memory cell array having identical layouts.

3. 发明公开

EP0797214A3 Semiconductor storage device 失效
公开(公告)号：EP0797214A3
公开(公告)日：1999-03-31
申请号：EP96110756.2
申请日：1996-07-03
申请人： SHARP KABUSHIKI KAISHA
发明人： Suminaga, Yasuo , Komatsu, Koji
IPC分类号： G11C17/12 , G11C7/00
CPC分类号： G11C11/5692 , G11C7/18 , G11C17/126
摘要： In a semiconductor storage device, a potential corresponding to a position of a word line selected from the memory cell array is applied to a bank selection line which is connected to the gate of a bank selection transistor, as an ON potential for the bank selection transistor so that it is possible to reduce the variation in the bit line potential depending upon the position of a memory cell in a bank of a ROM using a bank system.

4. 发明公开

EP0880144A2 Read only memory 失效
标题翻译： Festwertspeicher
公开(公告)号：EP0880144A2
公开(公告)日：1998-11-25
申请号：EP98304119.5
申请日：1998-05-26
申请人： Samsung Electronics Co., Ltd.
发明人： Choi, Byung-Sun
IPC分类号： G11C17/12 , G11C7/00
CPC分类号： G11C17/126 , G11C7/18
摘要： A read only memory has a plurality of blocks (BLK*) of memory cells, each block being associated with main bitlines (MBL*) and sub-bitlines (SB*). Sense amplifiers (SA*) are provided for reading information stored in the memory cells (M*) through the main bitlines. The memory has a block selection part (SSB*) disposed between adjacent blocks with a plurality of block selection transistors (STO*, STE*) for connecting the main bitlines to the sub-bitlines. The sub-bitlines extend to at least an adjacent block and are selectively connectable to the main bitlines through the block selection part.
摘要翻译：只读存储器具有存储器单元的多个块（BLK *），每个块与主位线（MBL *）和子位线（SB *）相关联。提供感测放大器（SA *），用于通过主位线读取存储在存储单元（M *）中的信息。存储器具有设置在相邻块之间的块选择部分（SSB *），其具有用于将主位线连接到子位线的多个块选择晶体管（STO *，STE *）。子位线延伸到至少相邻的块，并且可以通过块选择部分选择性地连接到主位线。

5. 发明公开

EP0783169A2 Matrix-Speicher (Virtual Ground) 失效
标题翻译： Matrix-Speicher（虚拟地面）
公开(公告)号：EP0783169A2
公开(公告)日：1997-07-09
申请号：EP96119168.1
申请日：1996-11-28
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Basse, Paul-Werner, von , Thewes, Roland, Dr. , Schmitt-Landsiedel, Doris, Dr. , Bollu, Michael, Dr.
IPC分类号： G11C17/12
CPC分类号： G11C8/10 , G11C17/126
摘要： Matrix-Speicher mit einer zeilenweisen und spaltenweisen Anordnung von Speichertransistoren (1), die über Wortleitungen (WL) und Bitleitungen (BL) adressiert werden können, und mit Steuertransistoren (2), die über Steuerleitungen (ST) angesteuert werden können und die jeweils alle Spalten des Zellenfeldes, d. h. die Bitleitungen, kurzschließen können mit Ausnahme der Spalte, in der sich eine auszulesende Speicherzelle befindet.
摘要翻译：矩阵存储器具有以行和列配置布置的存储晶体管（1），通过经由控制线（ST）寻址的字线（WL）和位线（BL）和控制晶体管（2）寻址。县。控制晶体管被配置为充当具有与设置有存储晶体管的位线对数相同数量的输出的二进制解码器，以及每个控制晶体管的相应控制线。

6. 发明公开

EP0601207A1 DATA READ METHOD AND READ ONLY MEMORY CIRCUIT 失效
标题翻译：数据读取方法和只读存储器电路
公开(公告)号：EP0601207A1
公开(公告)日：1994-06-15
申请号：EP93913597.6
申请日：1993-06-28
申请人： Oki Electric Industry Company, Limited
发明人： HARADA, Teruhiro Oki Electronic Industry Co. Ltd.
IPC分类号： G11C16/06 , G11C17/12
CPC分类号： G11C17/126 , G11C16/26
摘要： A given column line and a bit line adjacent to it are selected from a plurality of string lines (102-1 to 102-3) and bit lines (101-1 to 101-2) by the string selection signals (Y₁ to Y₃); and a given row line is selected from a plurality of row lines (103-1 to 103-n) by the row selection signals (X₀ to X n ). The data stored in the memory cells (104-01 to 104-n4) which are connected to the selected column line and row line are read out on the selected bit line. The selected column line is made to be at a first potential level (the potential level supplied from a constant-voltage circuit (160)). Substantially at the same time, the selected bit line is made to be at a second potential level (the potential level provided by a sense amplifying circuit (150)) which is lower than the first potential. The column lines which are not selected are made to be at a third potential level (the ground potential level or the potential level provided by a potential supply circuit (190)) which is lower than the second potential level. Then, the data are read out. Therefore, it is possible to read the data at a high speed, and further, to materialize a low power consumption because no reactive current flows.
摘要翻译：通过串选择信号（Y 1至Y 3）从多个串行（102-1至102-3）和位线（101-1至101-2）中选择给定的列线和与其相邻的位线， ; 并通过行选择信号（X 0至X n）从多个行线（103-1至103-n）中选择给定的行线。存储在连接到所选列线和行线的存储单元（104-01到104-n4）中的数据在所选位线上被读出。所选择的列线被制成处于第一电位电平（从恒压电路（160）提供的电位电平）。基本上同时，所选位线被设置为低于第一电位的第二电位电平（由读出放大电路（150）提供的电位电平）。未被选择的列线被制成处于比第二电位电平低的第三电位电平（地电位电平或由电位供给电路（190）提供的电位电平）。然后，数据被读出。因此，可以高速读取数据，并且进一步实现低功耗，因为没有无功电流流动。

7. 发明公开

EP0508588A2 Semiconductor read only memory 失效
标题翻译： Halbleiterfestwertspeicher。
公开(公告)号：EP0508588A2
公开(公告)日：1992-10-14
申请号：EP92301850.1
申请日：1992-03-04
申请人： SHARP KABUSHIKI KAISHA
发明人： Hotta, Yasuhiro
IPC分类号： G11C17/12
CPC分类号： G11C17/126 , G11C17/12
摘要： A semiconductor read only memory with hierarchical bit lines in which a resistance against a discharge current is constant irrespective of the position of a memory cell from which information is to be read is disclosed. A bank selecting MOSFET is connected to one end portion of a sub-bit line. Another bank selecting MOSFET is connected to the other end portion of the adjacent sub-bit line. Bank selecting MOSFETs are connected in the same alternate manner as described above. Therefore, since the resistance on bit lines against the read-out current is constant, a larger read-out current can be used especially when diffusion bit lines are used, whereby the semiconductor read only memory of the invention can achieve a high-speed read operation.
摘要翻译：公开了一种具有分级位线的半导体只读存储器，其中对于放电电流的电阻是恒定的，而与要读取信息的存储器单元的位置无关。存储体选择MOSFET连接到子位线的一个端部。另一组选择MOSFET连接到相邻子位线的另一端部分。银行选择MOSFET以与上述相同的交替方式连接。因此，由于针对读出电流的位线上的电阻是恒定的，所以特别是当使用扩散位线时可以使用更大的读出电流，由此本发明的半导体只读存储器可以实现高速读取操作。

8. 发明公开

EP0430191A2 Semiconductor memory 失效
标题翻译：半导体内存
公开(公告)号：EP0430191A2
公开(公告)日：1991-06-05
申请号：EP90122690.2
申请日：1990-11-27
申请人： SONY CORPORATION
发明人： Noda, Masanori
IPC分类号： G11C16/04 , G11C17/12
CPC分类号： H01L27/112 , G11C16/0491 , G11C17/126 , H01L27/115
摘要： In a semiconductor memory having word lines (12) and power source lines (13) such as bit lines, two word lines extending on both sides of each contact hole (14) of one of the power source lines (13) extending adjacent to each other extend between two adjacent contact holes (14) of the other power source line, which are staggered from the contact hole of the one power source line. A peripheral circuit of the semiconductor memory can be simplified although the memory is suitable for high-speed operation and high integration.
摘要翻译：在具有诸如位线的字线（12）和电源线（13）的半导体存储器中，两条字线在延伸到电源线（13）中的一条电源线（13）的每个接触孔（14）的两侧上延伸另一个电源线的两个相邻接触孔（14）之间延伸，与另一电源线的接触孔错开。尽管存储器适用于高速操作和高集成度，但可以简化半导体存储器的外围电路。

9. 发明公开

EP0188956A3 CMOS ROM data select circuit 失效
标题翻译： CMOS ROM数据选择电路
公开(公告)号：EP0188956A3
公开(公告)日：1989-02-22
申请号：EP85402564.0
申请日：1985-12-20
申请人： SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.)
发明人： Davis, Harold L.
IPC分类号： G11C17/00
CPC分类号： G11C17/126
摘要： © A data select circuit for selecting a column line in a CMOS ROM and for establishing a connection between a pair of bit lines and corresponding data lines uses a single NMOS pull-down transistor on the column line and a pair of P-channel pass transistors on the bit lines, the pass transistor gates being controlled not by an inverted column decode line, but by the column line itself, thus reducing the capaca- tive load on the column decoder and saving space.

10. 发明授权

EP0908896B1 A virtual ground type semiconductor storage device 有权
标题翻译：与虚拟接地的半导体存储器件
公开(公告)号：EP0908896B1
公开(公告)日：2005-02-09
申请号：EP98307448.5
申请日：1998-09-15
申请人： Sharp Kabushiki Kaisha
发明人： Ohta, Yoshiji
IPC分类号： G11C16/04 , G11C17/12
CPC分类号： G11C16/0491 , G11C17/126

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