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1. 发明授权

EP0508588B1 Semiconductor read only memory 失效
标题翻译：半导体只读存储器
公开(公告)号：EP0508588B1
公开(公告)日：1997-10-08
申请号：EP92301850.1
申请日：1992-03-04
申请人： SHARP KABUSHIKI KAISHA
发明人： Hotta, Yasuhiro
IPC分类号： G11C17/12
CPC分类号： G11C17/126 , G11C17/12

2. 发明授权

EP0482880B1 A read-only memory 失效
标题翻译：只读存储器
公开(公告)号：EP0482880B1
公开(公告)日：1996-06-05
申请号：EP91309738.2
申请日：1991-10-22
申请人： SHARP KABUSHIKI KAISHA
发明人： Hotta, Yasuhiro , Okada, Mikiro
IPC分类号： G11C17/12 , G11C7/00
CPC分类号： G11C17/126

3. 发明公开

EP0791931A3 Semiconductor memory device 失效
公开(公告)号：EP0791931A3
公开(公告)日：2003-07-23
申请号：EP96109985.0
申请日：1996-06-20
申请人： SHARP KABUSHIKI KAISHA
发明人： Hotta, Yasuhiro
IPC分类号： G11C7/00 , G11C16/06 , G11C7/10 , G11C7/06
CPC分类号： G11C7/1057 , G11C7/1051 , G11C16/26
摘要： The semiconductor memory device includes two sense amplifiers provided corresponding to data lines and a switching circuit for selectively connecting any two among the data lines to the two sense amplifiers, respectively. The data stored in one of the memory cells is amplified to be transmitted to an output buffer via the data line connected to one of the sense amplifiers. In parallel with this operation, the data stored in a next memory cell is amplified via the data line connected to another sense amplifier so as to be made valid. In this manner, after the data stored in one of the memory cell is transmitted to the output buffer, the data stored in the next memory cell is subsequently transmitted to the output buffer.

4. 发明授权

EP0509633B1 Semiconductor memory 失效
标题翻译：半导体内存
公开(公告)号：EP0509633B1
公开(公告)日：1995-01-18
申请号：EP92301917.8
申请日：1992-03-05
申请人： SHARP KABUSHIKI KAISHA
发明人： Hotta, Yasuhiro
IPC分类号： G06F11/20 , G11C8/00 , G11C16/00 , G11C17/00
CPC分类号： G11C29/76 , G11C8/00 , G11C16/00 , G11C17/10 , G11C29/822
摘要： The present invention provides a nonvolatile semiconductor memory that is partially rewritable. The present invention combines a large-capacity mask ROM with a small-capacity PROM between which selection is made for use as required.
摘要翻译：本发明提供了部分可重写的非易失性半导体存储器。本发明将大容量掩模ROM与小容量PROM组合，根据需要选择其中进行选择。

5. 发明公开

EP0508588A2 Semiconductor read only memory 失效
标题翻译： Halbleiterfestwertspeicher。
公开(公告)号：EP0508588A2
公开(公告)日：1992-10-14
申请号：EP92301850.1
申请日：1992-03-04
申请人： SHARP KABUSHIKI KAISHA
发明人： Hotta, Yasuhiro
IPC分类号： G11C17/12
CPC分类号： G11C17/126 , G11C17/12
摘要： A semiconductor read only memory with hierarchical bit lines in which a resistance against a discharge current is constant irrespective of the position of a memory cell from which information is to be read is disclosed. A bank selecting MOSFET is connected to one end portion of a sub-bit line. Another bank selecting MOSFET is connected to the other end portion of the adjacent sub-bit line. Bank selecting MOSFETs are connected in the same alternate manner as described above. Therefore, since the resistance on bit lines against the read-out current is constant, a larger read-out current can be used especially when diffusion bit lines are used, whereby the semiconductor read only memory of the invention can achieve a high-speed read operation.
摘要翻译：公开了一种具有分级位线的半导体只读存储器，其中对于放电电流的电阻是恒定的，而与要读取信息的存储器单元的位置无关。存储体选择MOSFET连接到子位线的一个端部。另一组选择MOSFET连接到相邻子位线的另一端部分。银行选择MOSFET以与上述相同的交替方式连接。因此，由于针对读出电流的位线上的电阻是恒定的，所以特别是当使用扩散位线时可以使用更大的读出电流，由此本发明的半导体只读存储器可以实现高速读取操作。

6. 发明授权

EP0586114B1 A semiconductor read only memory 失效
标题翻译：半导体读Nurspeicher
公开(公告)号：EP0586114B1
公开(公告)日：2001-11-14
申请号：EP93306303.4
申请日：1993-08-10
申请人： SHARP KABUSHIKI KAISHA
发明人： Hotta, Yasuhiro
IPC分类号： G06F11/20
CPC分类号： G11C29/822
摘要： A semiconductor read only memory is disclosed. The memory has a memory cell array including a plurality of memory cell groups. Each of the plurality of memory cell groups includes a plurality of memory cells. The memory has select circuit for selecting an arbitrary memory cell group from among the plurality of memory cell groups, and an address storage circuit for storing address information of an arbitrary one of the memory cell groups; and a data storage circuit for storing data to be written into the arbitrary one of the memory cell groups.

7. 发明授权

EP0560623B1 A semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：EP0560623B1
公开(公告)日：1999-12-01
申请号：EP93301888.9
申请日：1993-03-12
申请人： SHARP KABUSHIKI KAISHA
发明人： Hotta, Yasuhiro
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1051 , G11C7/22 , G11C8/06

8. 发明授权

EP0499460B1 Semiconductor memory device 失效
公开(公告)号：EP0499460B1
公开(公告)日：1997-12-03
申请号：EP92301171.2
申请日：1992-02-13
申请人： SHARP KABUSHIKI KAISHA
发明人： Hotta, Yasuhiro
IPC分类号： G11C7/06 , G11C17/12 , G11C11/419 , G11C16/06
CPC分类号： G11C16/26 , G11C7/06 , G11C11/419 , G11C17/12

9. 发明授权

EP0521594B1 Semiconductor memory device 失效
公开(公告)号：EP0521594B1
公开(公告)日：1997-05-07
申请号：EP92301161.3
申请日：1992-02-12
申请人： SHARP KABUSHIKI KAISHA
发明人： Hotta, Yasuhiro
IPC分类号： G11C17/18
CPC分类号： G11C17/12

10. 发明授权

EP0480752B1 Semiconductor memory device with short circuit identifying means 失效
标题翻译：一种半导体存储器件，包括：用于识别短路
公开(公告)号：EP0480752B1
公开(公告)日：1997-02-05
申请号：EP91309384.5
申请日：1991-10-11
申请人： SHARP KABUSHIKI KAISHA
发明人： Hotta, Yasuhiro
IPC分类号： G11C29/00
CPC分类号： G11C29/34 , G11C29/50
摘要： A semiconductor memory device such as a ROM is provided with a word line test circuit and a word line drive circuit. The word line test circuit outputs a high level signal when a test signal is applied and a low level signal when the test signal is not applied. The word line drive circuit drives the respective word lines in the memory cell array, and is connected to the output of the word line test circuit, so that when driving one group of word lines (either the odd-numbered word lines or the even-numbered word lines), a high level signal is applied to the one group of word lines, and when not driving the one group of word lines, a low level signal is applied to the one group of word lines. On the other hand, when driving the other group of word lines, a high level signal is applied to the other group of word lines, and when not driving the other group of word lines, the output signal from the word line test circuit is applied to the other group of word lines, thereby enabling short circuits between adjacent word lines to be identified quickly. A bit line test switch circuit is provided which is connected to the bit lines in the memory cell array. In response to a test signal, the bit line test switch circuit applies signals of different levels to the odd-numbered and even-numbered bit lines respectively, and short circuits between adjacent bit lines can be identified quickly.

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