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1. 发明公开

EP0712205A2 Fixed-interval timing circuit and method 失效
标题翻译： Zeitschaltung mit festem Intervall
公开(公告)号：EP0712205A2
公开(公告)日：1996-05-15
申请号：EP95307803.7
申请日：1995-11-01
申请人： AT&T Corp.
发明人： Shoji, Masakazu
IPC分类号： H03K5/13
CPC分类号： H03K5/13
摘要： A system and method generates a signal (on 132) having a reliable, fixed duration and/or delay as a function of relative, not absolute, device (114,115) characteristics. That is to say, the time period of the generated signal is determined as a ratio of one device's (114) operating characteristics to another device's (115) operating characteristics. In particular, the invention provides a fixed time signal as a function of the relative values of two capacitive elements (114,115) that have a known ratio of capacitance with respect to each other. The invention is particularly useful when implemented upon an integrated circuit, as standard fabrication techniques for such circuits allow relative device characteristics to be held to relatively tight tolerances.
摘要翻译：系统和方法产生具有作为相对而不是绝对的（114,115）特性的函数的可靠的，固定的持续时间和/或延迟的信号（在132上）。也就是说，所生成的信号的时间周期被确定为一个设备的（114）操作特性与另一设备的（115）操作特性的比率。特别地，本发明提供固定的时间信号作为相对于彼此具有已知的电容比的两个电容元件（114,115）的相对值的函数。当在集成电路上实现本发明时，本发明是特别有用的，因为用于这种电路的标准制造技术允许将相对器件特性保持在相对严格的公差。

2. 发明公开

EP0701258A1 Integrated circuit memory device 失效
标题翻译：集成电路存储器件
公开(公告)号：EP0701258A1
公开(公告)日：1996-03-13
申请号：EP95306062.1
申请日：1995-08-30
申请人： AT&T Corp.
发明人： Shoji, Masakazu
IPC分类号： G11C11/56 , G11C17/00
CPC分类号： G11C17/00 , G11C11/56 , G11C11/565 , G11C11/5692
摘要： The present invention comprises a novel memory circuit wherein a plurality of memory cells have passive impedance values representative of the information stored therein. In the circuit, a signal source having a plurality of outputs is operable to provide a sequence of read signals, one signal per output. Each of the plurality of outputs is connected to one of a plurality of memory cells. Each memory cell comprises an impedance element, its impedance value representative of the data value stored therein. All of the memory cells are thereafter connected to a sum line and a read out circuit. When the signal source provides one of the sequence signals to one of the memory cell impedance elements, it affects the signal on the sum line in a manner that is related to the impedance value of the memory cell. By applying each signal in the sequence to a different impedance element, the voltage on the sum line is directly affected by each of the impedance elements in sequence. The read out circuit transforms the read out circuit voltage into a voltage level proportional or otherwise indicative of each impedance value, and thus the stored data, in sequence.
摘要翻译：本发明包括一种新颖的存储电路，其中多个存储单元具有代表存储在其中的信息的无源阻抗值。在该电路中，具有多个输出的信号源可操作以提供一系列读取信号，每个输出一个信号。多个输出中的每一个都连接到多个存储单元中的一个。每个存储器单元包括阻抗元件，其阻抗值代表存储在其中的数据值。所有的存储单元此后连接到总和线和读出电路。当信号源将一个序列信号提供给一个存储单元阻抗元件时，它以与存储单元的阻抗值有关的方式影响和线上的信号。通过将序列中的每个信号施加到不同的阻抗元件，总和线上的电压直接受到每个阻抗元件的顺序影响。读出电路将读出的电路电压转换成与每个阻抗值成比例的或以其他方式指示每个阻抗值的电压电平，并且因此将存储的数据依次表示。

3. 发明公开

EP0657893A3 High-density read-only data storage 失效
标题翻译：高密度只读数据存储
公开(公告)号：EP0657893A3
公开(公告)日：1995-11-22
申请号：EP94308848.4
申请日：1994-11-30
申请人： AT&T Corp.
发明人： Shoji, Masakazu
IPC分类号： G11C17/12 , H01L27/112 , H01L21/8246
CPC分类号： H01L27/11273 , G11C17/12 , H01L27/112
摘要： A read-only memory ("ROM") utilizing junction field-effect transistors ("JFETs") each having a conductive channel (107,108) orthogonally oriented with respect to the surface of the semiconductor material (101,102,104) composing the JFET. A fixed-position ion beam is employed to create this narrow gate channel, which extends between the JFET's source (104) and drain contact (e.g. 105). Employing such JFETs as basic memory sites within a semiconductor ROM circuit allows for an architecture that conforms to a minimum lattice structure layout. In addition, the resulting ROM offers high speed access of data. Although JFETs have not been utilized as the transistor of choice within ROMs because of their seemingly inferior performance when compared to MOSFETs, the invention provides a novel architecture which significantly enhances the practicality of the JFET as a memory device.
摘要翻译：一种利用结型场效应晶体管（“JFET”）的只读存储器（“ROM”），每个晶体管具有相对于组成JFET的半导体材料（101,102,104）的表面正交定向的导电沟道（107,108）。使用固定位置的离子束来形成该狭窄的栅极沟道，其在JFET的源极（104）和漏极接触（例如105）之间延伸。在半导体ROM电路内采用这种JFET作为基本存储器位置允许符合最小栅格结构布局的架构。另外，由此产生的ROM提供高速访问数据。尽管JFET没有被用作ROM内选择的晶体管，因为与MOSFET相比，它们的性能似乎较差，本发明提供了一种新颖的架构，其显着增强了JFET作为存储器件的实用性。

4. 发明公开

EP0297778A2 Apparatus including resonant-tunneling device having multiple-peak current-voltage characteristics 失效
标题翻译：设备与谐振隧穿效应器件，其电流 - 电压特性具有多个尖端。
公开(公告)号：EP0297778A2
公开(公告)日：1989-01-04
申请号：EP88305716.8
申请日：1988-06-22
申请人： AT&T Corp.
发明人： Capasso, Federico , Yi Cho, Alfred , Sen, Susanta , Shoji, Masakazu , Sivco, Deborah
IPC分类号： H01L27/06 , H01L29/88 , H01L29/205
CPC分类号： B82Y10/00 , G11C11/56 , G11C2211/5614 , H01L29/7606 , H01L29/882 , H03B19/16
摘要： A semiconductor integrated resonant-tunneling device having multiple negative-resistance regions, and having essentially equal current peaks in such regions, is useful as a highly compact element, e.g., in apparatus designed for ternary logic operations, frequency multiplication, waveform scrambling, memory operation, parity-bit generation, and coaxial-line driving. The device can be made by layer deposition on a substrate and includes a resonant-tunneling structure between contacts such that side-by-side first and third contacts are on one side, and a second contact is on the opposite side of the resonant-tunneling structure.
摘要翻译：，波形加扰的半导体集成电路谐振隧穿装置具有多个负电阻区，以及具有在搜索区域基本上等于电流峰值，是作为高度紧凑的元件，例如，在设备设计成用于三值逻辑运算，倍频，存储器操作有用，奇偶校验位的生成，和同轴线驱动。该装置可以通过层沉积在一个基片制成，并包括搜索联系人之间的谐振隧穿结构做侧由端的第一和第三接触是在一侧上，并且第二接触是在谐振隧穿的相对侧结构。

5. 发明公开

EP0662659A1 Method for minimizing the effect of memory errors within a digital information storage system 失效
标题翻译：信徒数字信息系统中的Verfahren zur Minimierung des Effekts von Speicherfehlern。
公开(公告)号：EP0662659A1
公开(公告)日：1995-07-12
申请号：EP94309353.4
申请日：1994-12-14
申请人： AT&T Corp.
发明人： Shoji, Masakazu
IPC分类号： G06F11/00
CPC分类号： G11C29/88 , G11C17/123 , G11C29/52
摘要： A method is disclosed for the retrieval of digital information from a memory device wherein data representing temporally proximate samplings of a signal, or band-adjacent frequency components of a signal are stored in separate memory locations (132-137), each separate memory location being subject to circuit failure independent of other such memory locations. The effects of errors caused by memory circuit failures within the digital data system are reduced by testing for data losses upon retrieval of the information. In response to detecting a loss (e.g. in 132), data representing a signal sampling temporally proximate (e.g. in 133) to the signal sampling represented by the lost data is substituted for the lost data. In yet another method of the invention, a similar testing/substitution scheme is employed to reduce the effects of memory circuit failure errors. However, in response to detecting a data loss, data representing a frequency component adjacent to the band of the frequency component represented by the lost data is substituted for the lost data.
摘要翻译：公开了一种用于从存储器件检索数字信息的方法，其中表示信号的时间上接近的采样的数据或信号的频带相邻频率分量被存储在单独的存储器位置（132-137）中，每个单独的存储器位置受其他这种存储器位置的电路故障影响。数字数据系统中由于存储器电路故障引起的错误的影响通过在检索信息时测试数据丢失来减少。响应于检测到丢失（例如在132），表示对由丢失数据表示的信号采样在时间上接近（例如，133）的信号的数据代替丢失的数据。在本发明的另一种方法中，采用类似的测试/替代方案来减少存储器电路故障误差的影响。然而，响应于检测到数据丢失，表示与由丢失数据表示的频率分量的频带相邻的频率分量的数据被替换为丢失的数据。

6. 发明公开

EP0459715A3 Integrated circuits which compensate for local conditions 失效
标题翻译：对本地条件进行补偿的集成电路
公开(公告)号：EP0459715A3
公开(公告)日：1993-05-19
申请号：EP91304720.5
申请日：1991-05-24
申请人： AT&T Corp.
发明人： Shoji, Masakazu
IPC分类号： G05F3/24 , G05F1/46 , H03K19/003
CPC分类号： H03K19/00361 , G05F3/24 , H03K19/00384
摘要： Apparatus for compensating for the effect of a local condition on an active element (105,117,119) in a portion (203) of an integrated circuit (301) includes a detecting element (205) in the portion of the integrated circuit which is subject to the local condition for producing a response to the local condition which is proportional to the local condition's effect on the active element, and a compensation element (207) which is coupled to the detecting element and to the portion for reacting to the response of the detecting element to the local condition by providing a compensating input to the portion which is proportional to the response and which compensates for the local condition's effect on the active element. An embodiment of the apparatus which compensates for leakage currents in FETs in a dynamic CMOS integrated circuit employs one or more FETs (302,309) which are interspersed among active FETs as the detecting element and a current mirror (307) as the compensating element. The current mirror responds to the leakage current in the detecting element FETs by producing a compensating current to compensate for the leakage current in the active FETs. The embodiment is employed in a dynamic NOR gate and a dynamic PLA.

7. 发明授权

EP0459715B1 Integrated circuits which compensate for local conditions 失效
标题翻译：当地的条件补偿集成电路
公开(公告)号：EP0459715B1
公开(公告)日：1997-08-20
申请号：EP91304720.5
申请日：1991-05-24
申请人： AT&T Corp.
发明人： Shoji, Masakazu
IPC分类号： G05F3/24 , G05F1/46 , H03K19/003
CPC分类号： H03K19/00361 , G05F3/24 , H03K19/00384

8. 发明公开

EP0265047A1 Dual domino CMOS logic circuit, including complementary vectorization and integration 失效
标题翻译： Doppel-Domino-CMOS-Logikschaltung mit BildungkomplementärerVektoren und deren Integration。
公开(公告)号：EP0265047A1
公开(公告)日：1988-04-27
申请号：EP87307270.6
申请日：1987-08-18
申请人： AT&T Corp.
发明人： Shoji, Masakazu
IPC分类号： H03K19/096 , H03K19/21
CPC分类号： H03K19/0963 , H03K19/215
摘要： At each stage of a domino CMOS logic circuit, the output signal Y 1 and its inversion Y are separately generated in mutually complementary first and second logic networks in each such stage. These outputs are then used as inputs for succeeding domino logic stages. In this way, all inputs are guaranteed to be low at the end of the precharging phase as is desired for all inputs to all domino logic.
摘要翻译：在多米诺CMOS逻辑电路的每个阶段，输出信号Y1及其反相@ 1分别在每个这样的级中相互互补的第一和第二逻辑网络中产生。然后将这些输出用作后续的多米诺逻辑阶段的输入。以这种方式，在预充电阶段结束时，所有输入都保证为低电平，因为对所有多米诺骨牌逻辑的所有输入都是需要的。

9. 发明公开

EP0133359A2 Chipset synchronization arrangement 失效
标题翻译：装置用于同步芯片组件。
公开(公告)号：EP0133359A2
公开(公告)日：1985-02-20
申请号：EP84305107.9
申请日：1984-07-27
申请人： AT&T Corp.
发明人： Shoji, Masakazu
IPC分类号： G06F1/04
CPC分类号： G06F13/4217 , G06F1/10
摘要： Each chip (11, 12) of a microprocessor chipset is synchronized by an associated controller (400) which adjusts a control signal (202) for controlling the delay of a variable delay circuit during each operating cycle. The controller tailors the control signal for each chip by an op-amp (507) which compares the output of an internal clock in each chip with a reference system voltage (508).

10. 发明公开

EP0657893A2 High-density read-only data storage 失效
标题翻译： Nur-Lesespeicher von hoher Dichte。
公开(公告)号：EP0657893A2
公开(公告)日：1995-06-14
申请号：EP94308848.4
申请日：1994-11-30
申请人： AT&T Corp.
发明人： Shoji, Masakazu
IPC分类号： G11C17/12 , H01L27/112 , H01L21/8246
CPC分类号： H01L27/11273 , G11C17/12 , H01L27/112
摘要： A read-only memory ("ROM") utilizing junction field-effect transistors ("JFETs") each having a conductive channel (107,108) orthogonally oriented with respect to the surface of the semiconductor material (101,102,104) composing the JFET. A fixed-position ion beam is employed to create this narrow gate channel, which extends between the JFET's source (104) and drain contact (e.g. 105). Employing such JFETs as basic memory sites within a semiconductor ROM circuit allows for an architecture that conforms to a minimum lattice structure layout. In addition, the resulting ROM offers high speed access of data. Although JFETs have not been utilized as the transistor of choice within ROMs because of their seemingly inferior performance when compared to MOSFETs, the invention provides a novel architecture which significantly enhances the practicality of the JFET as a memory device.
摘要翻译：每个具有相对于组成JFET的半导体材料（101,102,104）的表面正交取向的导电沟道（107,108）的结型场效应晶体管（“JFET”）的只读存储器（“ROM”）。使用固定位置离子束来产生在JFET源极（104）和漏极触点（例如105）之间延伸的窄栅极沟道。将这种JFET作为半导体ROM电路内的基本存储器位置允许符合最小格子结构布局的架构。此外，所得到的ROM提供数据的高速访问。虽然JFET与MOSFET相比，由于其与MOSFET相比性能较差，因此在ROM中尚未使用JFET作为选择晶体管，本发明提供了一种新颖的架构，可显着增强JFET作为存储器件的实用性。

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