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1. 发明公开

EP3345186A4 APPARATUS AND METHODS INCLUDING ESTABLISHING A NEGATIVE BODY POTENTIAL IN A MEMORY CELL 有权转让
公开(公告)号：EP3345186A4
公开(公告)日：2018-07-25
申请号：EP17788092
申请日：2017-08-09
申请人： MICRON TECHNOLOGY INC
发明人： SAKUI KOJI , HAWES MARK , TANZAWA TORU , BINFET JEREMY
IPC分类号： G11C16/34 , G11C7/04 , G11C16/04 , G11C16/08 , G11C16/14 , G11C16/20 , G11C16/26 , G11C16/30 , G11C16/32 , H01L27/115 , H01L27/11514
CPC分类号： G11C16/26 , G11C7/04 , G11C16/0483 , G11C16/08 , G11C16/14 , G11C16/20 , G11C16/30 , G11C16/32 , G11C16/3418 , G11C16/3427 , H01L27/115
摘要： Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell prior to initiating a sensing operation on the memory cell, in response to a timer, or during an access operation of another memory cell.

2. 发明公开

EP3347899A1 FLASH MEMORY SYSTEM USING DUMMY MEMORY CELL AS SOURCE LINE PULL DOWN CIRCUIT 有权
公开(公告)号：EP3347899A1
公开(公告)日：2018-07-18
申请号：EP16758011.7
申请日：2016-08-12
申请人： Silicon Storage Technology Inc.
发明人： BAI, Ning , TRAN, Hieu, Van , RAO, Qing , GHAZAVI, Parviz , YUE, Kai, Man
IPC分类号： G11C16/04 , G11C16/08
CPC分类号： G11C16/28 , G11C7/14 , G11C16/0425 , G11C16/08 , G11C16/14 , G11C16/30 , G11C2216/04
摘要： The present invention relates to a flash memory device that uses dummy memory cells as source line pull down circuits. In one embodiment, when a memory cell is in read mode or erase mode, its source line is coupled to ground through a bitline of a dummy memory cell, which in turn is coupled to ground. When the memory cell is in program mode, the bitline of the dummy memory cell is coupled to an inhibit voltage, which places the dummy memory cell in a program inhibit mode that maintains the dummy memory cell in erased state.

3. 发明公开

EP3128517A4 SEMICONDUCTOR DEVICE, PRE-WRITE PROGRAM, AND RESTORATION PROGRAM 审中-公开
公开(公告)号：EP3128517A4
公开(公告)日：2018-03-14
申请号：EP14846736
申请日：2014-03-31
申请人： RENESAS ELECTRONICS CORP
发明人： TANI KUNIO
IPC分类号： G11C16/14 , G11C16/04 , G11C16/10 , G11C16/22 , G11C16/28 , G11C16/34
CPC分类号： G11C16/14 , G11C16/0416 , G11C16/0425 , G11C16/0475 , G11C16/10 , G11C16/105 , G11C16/107 , G11C16/22 , G11C16/28 , G11C16/344 , G11C16/3445 , G11C16/3477
摘要： When a control circuit (105) has received a first erase command, the control circuit (105) controls performing a first pre-write process to allow a first storage device (102) and a second storage device (103) to have threshold voltages, respectively, both increased, and the control circuit (105) thereafter controls performing an erase process to allow the first storage device (102) and the second storage device (103) to have their respective threshold voltages both decreased to be smaller than a prescribed erase verify level. When the control circuit (105) has received a second erase command, the control circuit (105) controls performing a second pre-write process to allow one of the first storage device (102) and the second storage device (103) to have its threshold voltage increased, and control circuit (105) subsequently controls performing the erase process.

4. 发明公开

EP3259758A1 FLASH MEMORY DEVICE CONFIGURABLE TO PROVIDE REAL ONLY MEMORY FUNCTIONALITY 有权转让
标题翻译：闪存设备可配置为提供真正的内存功能
公开(公告)号：EP3259758A1
公开(公告)日：2017-12-27
申请号：EP16706086.2
申请日：2016-02-03
申请人： Silicon Storage Technology Inc.
发明人： TRAN, Hieu, Van , LY, Anh , VU, Thuan , NGUYEN, Hung, Quoc
IPC分类号： G11C16/22
CPC分类号： G11C16/08 , G11C16/14 , G11C16/22 , G11C16/26 , G11C17/08 , G11C2216/26
摘要： The disclosed embodiments comprise a flash memory device that can be configured to operate as a read only memory device. In some embodiments, the flash memory device can be configured into a flash memory portion and a read only memory portion.

5. 发明公开

EP3210236A1 IMPROVEMENTS RELATING TO ELECTRONIC MEMORY DEVICES 审中-公开
标题翻译：有关电子记忆装置的改进
公开(公告)号：EP3210236A1
公开(公告)日：2017-08-30
申请号：EP15791725.3
申请日：2015-10-23
申请人： Lancaster University Business Enterprises Limited
发明人： HAYNE, Manus
IPC分类号： H01L21/28 , H01L29/423 , H01L29/66 , H01L29/788 , H01L29/80
CPC分类号： H01L29/803 , G11C16/14 , G11C16/28 , H01L21/28273 , H01L29/42324 , H01L29/432 , H01L29/66916 , H01L29/66924
摘要： A memory cell for storing one or more bits of information has a control gate, a source terminal and a drain terminal. A semiconductor substrate is located between the source and drain terminals, and a floating gate is disposed between the control gate and the semiconductor substrate. The floating gate is electrically isolated from the control gate by a charge trapping barrier, and is electrically isolated from the semiconductor substrate by a charge blocking barrier. At least one of the charge trapping barrier and the charge blocking barrier contains a III-V semiconductor material. The charge trapping barrier is adapted to enable the selective passage of charge carriers between the control gate and the floating gate, in use, to modify the one or more bits of information stored by the memory cell.
摘要翻译：用于存储一个或多个信息位的存储器单元（10）具有控制栅极（24），源极端子（12）和漏极端子（14）。半导体衬底（16）位于源极（12）和漏极（14）端子之间，并且浮置栅极（26）设置在控制栅极（24）和半导体衬底（16）之间。浮动栅极（26）通过电荷俘获阻挡层（30）与控制栅极（24）电隔离，并且通过电荷阻挡阻挡层（28）与半导体衬底（16）电隔离。电荷俘获阻挡层（30）和电荷阻挡阻挡层（28）中的至少一个含有III-V族半导体材料。电荷捕捉屏障（30）适于使得在使用中控制栅极（24）和浮动栅极（26）之间的电荷载流子的选择性通过能够修改存储器单元所存储的一个或多个信息位（ 10）。

6. 发明公开

EP3201926A1 A NON-VOLATILE SPLIT GATE MEMORY DEVICE AND A METHOD OF OPERATING SAME 审中-公开
标题翻译：一种非易失性分裂栅极存储器件及其操作方法
公开(公告)号：EP3201926A1
公开(公告)日：2017-08-09
申请号：EP15771380.1
申请日：2015-09-14
申请人： Silicon Storage Technology Inc.
发明人： TRAN, Hieu, Van , NGUYEN, Hung, Quoc , DO, Nhan
IPC分类号： G11C16/04 , G11C16/12
CPC分类号： G11C16/24 , G11C16/0408 , G11C16/0425 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26
摘要： A non-volatile memory device that a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. A negative charge pump circuit generates a first negative voltage. A control circuit receives a command signal and generates a plurality of control signals, in response thereto and applies the first negative voltage to the word line of the unselected memory cells. During the operations of program, read or erase, a negative voltage can be applied to the word lines of the unselected memory cells.
摘要翻译：第一导电类型的半导体衬底的非易失性存储器件。非易失性存储器单元阵列位于以多行和多列排列的半导体衬底中。每个存储器单元包括在第二导电类型的半导体衬底的表面上的第一区域和在第二导电类型的半导体衬底的表面上的第二区域。沟道区域在第一区域和第二区域之间。字线覆盖沟道区的第一部分并且与其绝缘，并且与第一区相邻并且与第一区几乎没有或没有重叠。浮置栅极覆盖沟道区域的第二部分，与第一部分相邻，并与其绝缘并与第二区域相邻。耦合栅极覆盖浮动栅极。位线连接到第一区域。负电荷泵电路产生第一负电压。控制电路接收命令信号并响应于此产生多个控制信号，并将第一负电压施加到未选存储单元的字线。在编程操作期间，读取或擦除操作期间，负电压可施加到未被选择的存储器单元的字线。

7. 发明公开

EP3196883A1 MEMORY ARRAY CAPABLE OF PERFORMING BYTE ERASE OPERATION 有权转让
标题翻译：存储阵列能够执行字节擦除操作
公开(公告)号：EP3196883A1
公开(公告)日：2017-07-26
申请号：EP16175005.4
申请日：2016-06-17
申请人： eMemory Technology Inc.
发明人： Lai, Tsung-Mu , Chen, Chih-Hsin , Wang, Shih-Chen , Po, Chen-Hao
IPC分类号： G11C16/04 , G11C8/12 , G11C16/14 , G11C16/12 , H01L27/11558
CPC分类号： G11C16/30 , G11C7/065 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/10 , G11C16/0408 , G11C16/0433 , G11C16/0458 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , G11C16/24 , G11C16/26 , H01L23/528 , H01L27/0207 , H01L27/11517 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11558 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/1095 , H01L29/42328
摘要： A memory array (10) includes a plurality of memory pages (MP1 to MPM), each memory page includes a plurality of memory byte units (MB 1,1 to MB M,N ), each memory byte unit includes a plurality of memory cells (100 1,1,1 to 100 M,N,K ,) and each memory cell includes a floating gate module (110), a control element (120), and an erase element (130). Each memory byte unit (MB 1 , 1 ) designates a group of k memory cells connected to a subset of k bit lines (BL 1,1 ,,..BL 1,k ) and to a corresponding word line (WL1), wherein memory byte units (MB 1 , 1 to MB M,1 or MB 1 , N to MB M,N , MB' 1 , 1 to MB' M,1 or MB' 1 , N to MB' M,N ) connected to a same corresponding subset of k bit lines (BL1,1 to BL1,k or BLN,1 to BLN,K) are coupled to a same corresponding erase line (EL1 or ELN); and memory byte units (MB 1 , 1 to MB 1 , N or MB M , 1 to MB M , N , MB' 1 , 1 to MB' 1,N , or MB' M , 1 to MB' M , N ) connected to different corresponding subsets of k bit lines (BL1,1 to BL1,k , BLN,1 to BLN,K) are coupled to different corresponding erase lines (EL1 to ELN). Therefore, the memory array (10) is able to support byte operations while the memory cells of the same memory byte can share the same wells. The circuit area of the memory array (10) can be reduced and the operation of the memory array (10) can be more flexible.
摘要翻译：存储器阵列（10）包括多个存储器页（MP1到MPM），每个存储器页包括多个存储器字节单元（MB1,1到MBM，N），每个存储器字节单元包括多个存储器单元（1001 ，1,1至100M，N，K），并且每个存储器单元包括浮动栅极模块（110），控制元件（120）和擦除元件（130）。每个存储器字节单元（MB1,1）指定连接到k个位线（BL1,1，...，BL1，k）的子集并且与相应的字线（WL1）连接的k个存储器单元的组，其中存储器字节单元（MB1,1到MBM，1或MB1，N到MBM，N，MB'1,1到MB'M，1或MB'1，N到MB'M，N）连接到k个位线的相同对应子集（BL1,1到BL1，k或BLN，1到BLN，K）耦合到相同的对应擦除线（EL1或ELN）; 和存储器字节单元（MB1,1至MB1，N或MBM，1至MBM，N，MB'1,1至MB'1，N或MB'M，1至MB'M，N） k条位线（BL1,1到BL1，k，BLN，1到BLN，K）的子集连接到不同的对应擦除线（EL1到ELN）。因此，存储器阵列（10）能够支持字节操作，而同一存储器字节的存储器单元可以共享相同的阱。存储器阵列（10）的电路面积可以减小并且存储器阵列（10）的操作可以更灵活。

8. 发明公开

EP3152669A1 REMOVABLE MEMORY CARD TYPE DETECTION SYSTEMS AND METHODS 有权
标题翻译：系统维也纳ZER ERKENNUNG ENTNEHMBARER SPEICHERKARTEN
公开(公告)号：EP3152669A1
公开(公告)日：2017-04-12
申请号：EP15745589.0
申请日：2015-06-02
申请人： Qualcomm Incorporated
发明人： SHIN, Hyunsuk , SANCHEZ, Henry, Laurel , VUONG, Hung, Quoc , GIL, Amit
IPC分类号： G06F13/40 , G06K13/067 , G06K19/077
CPC分类号： G06F13/4022 , G06F13/4068 , G06F13/4234 , G11C16/14 , G11C16/20 , G11C16/34
摘要： Removable memory card type detection systems and methods are disclosed. In one aspect, a removable memory card is inserted into a receptacle of a host. The host determines a type of removable memory card based upon either electrical or physical properties of the removable memory card. In this manner, if the host detects that the removable memory card possesses certain electrical or physical properties associated with a microSD card, the host determines that the removable memory card is a microSD type card. If the host detects that the removable memory card possesses certain electrical or physical properties associated with a UFS card, the host determines that the removable memory card is a UFS type card. By determining the card type based on detection of certain electrical or physical properties, aspects disclosed herein are able to distinguish between UFS and microSD cards without requiring an additional pin or card initialization time.
摘要翻译：公开了可移动存储卡型检测系统和方法。在一个方面，可移动存储卡插入到主机的插座中。主机根据可移动存储卡的电气或物理属性确定一种可移动存储卡。以这种方式，如果主机检测到可移动存储卡具有与microSD卡相关联的某些电气或物理属性，则主机确定可移动存储卡是microSD型卡。如果主机检测到可移动存储卡具有与UFS卡相关联的某些电气或物理属性，则主机确定可移动存储卡是UFS型卡。通过基于某些电或物理特性的检测确定卡类型，本文公开的方面能够区分UFS和microSD卡，而不需要额外的引脚或卡初始化时间。

9. 发明公开

EP3128517A1 SEMICONDUCTOR DEVICE, PRE-WRITE PROGRAM, AND RESTORATION PROGRAM 审中-公开
标题翻译：半导体器件，预写程序和恢复程序
公开(公告)号：EP3128517A1
公开(公告)日：2017-02-08
申请号：EP14846736.8
申请日：2014-03-31
申请人： Renesas Electronics Corporation
发明人： TANI, Kunio
IPC分类号： G11C16/02 , G11C16/04
CPC分类号： G11C16/14 , G11C16/0416 , G11C16/0425 , G11C16/0475 , G11C16/10 , G11C16/105 , G11C16/107 , G11C16/22 , G11C16/28 , G11C16/344 , G11C16/3445 , G11C16/3477
摘要： When a control circuit (105) has received a first erase command, the control circuit (105) controls performing a first pre-write process to allow a first storage device (102) and a second storage device (103) to have threshold voltages, respectively, both increased, and the control circuit (105) thereafter controls performing an erase process to allow the first storage device (102) and the second storage device (103) to have their respective threshold voltages both decreased to be smaller than a prescribed erase verify level. When the control circuit (105) has received a second erase command, the control circuit (105) controls performing a second pre-write process to allow one of the first storage device (102) and the second storage device (103) to have its threshold voltage increased, and control circuit (105) subsequently controls performing the erase process.
摘要翻译：当控制电路（105）接收到第一擦除命令时，控制电路（105）控制执行第一预写入过程以允许第一存储设备（102）和第二存储设备（103）具有阈值电压，所述第一存储装置（102）和所述第二存储装置（103）的各自的阈值电压均减小到小于规定的擦除量，并且所述控制电路（105）随后控制执行擦除处理以允许所述第一存储装置（102）和所述第二存储装置验证等级。当控制电路（105）接收到第二擦除命令时，控制电路（105）控制执行第二预写入过程以允许第一存储装置（102）和第二存储装置（103）中的一个使其第一存储装置阈值电压增加，并且控制电路（105）随后控制执行擦除处理。

10. 发明公开

EP2912665A4 PARTIAL PAGE MEMORY OPERATIONS 有权
标题翻译：部分页面存储器操作
公开(公告)号：EP2912665A4
公开(公告)日：2016-06-29
申请号：EP13848265
申请日：2013-10-25
申请人： MICRON TECHNOLOGY INC
发明人： ABRAHAM MICHAEL , TANAKA TOMOHARU , KAWAI KOICHI , EINAGA YUICHI
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10
CPC分类号： G11C16/107 , G06F12/0246 , G06F2212/7201 , G11C16/0483 , G11C16/10 , G11C16/14
摘要： Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data lines shared by the strings, with the access lines coupled to the memory cells corresponding to a respective tier of the plurality of tiers. The memory cells corresponding to at least a portion of the respective tier may comprise a respective page of a plurality of pages. Subsets of the data lines may be mapped into a respective partial page of a plurality of partial pages of the respective page. Each partial page may be independently selectable from other partial pages. Additional apparatuses and methods are disclosed.

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