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1. 发明公开

EP0467361A1 BICMOS gate array device 失效
标题翻译： BICMOS门阵列-Anordnung。
公开(公告)号：EP0467361A1
公开(公告)日：1992-01-22
申请号：EP91112025.1
申请日：1991-07-18
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nagamatsu, Tetsu , Momose, Hiroshi
IPC分类号： H01L27/118 , H01L27/07
CPC分类号： H01L27/11896
摘要： A semiconductor device has a plurality of basic cells fabricated on a single semiconductor substrate. Each of the basic cells comprises a first-conduction-type FETs (P3, P4; P5, P6), a second-conduction-type FETs (N3, N4; N5, N6), and a bipolar transistor (2, 4, 5). The collector region of the bipolar transistor is formed in a well region (2) where the first-conduction-type FETs are formed. The bipolar transistor is formed between the first-conduction-type FETs of adjacent ones of the basic cells separated by an element insulation film.
摘要翻译：半导体器件具有制造在单个半导体衬底上的多个基本单元。每个基本单元包括第一导电型FET（P3，P4; P5，P6），第二导电型FET（N3，N4; N5，N6）和双极晶体管（2,4,5 ）。双极晶体管的集电极区域形成在其中形成第一导电型FET的阱区（2）中。双极晶体管形成在由元件绝缘膜隔开的相邻的基本单元的第一导电型FET之间。

2. 发明公开

EP0444524A1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：EP0444524A1
公开(公告)日：1991-09-04
申请号：EP91102499.0
申请日：1991-02-21
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Hara, Hiroyuki , Watanabe, Yoshinori
IPC分类号： G11C7/00 , G11C17/12
CPC分类号： H01L27/11896 , G11C7/1048 , G11C7/12 , G11C17/12
摘要： Disclosed is a semiconductor integrated circuit of a bipolar CMOS gate array type having a plurality of basic cells (8, 9, 10, and11)arranged in a matrix, each of which comprising MOS transistors (P1 to P4 and N1 to N4) as memory cells, a bipolar transistor (NPN1), and a resistance (R1) and bit lines for transferring data stored in the memory cells to the outside, and the semiconductor integrated circuit is characterized by that the basic cells (8, 9, 10, and 11) are grouped into a plurality of blocks (BLOCK A and BLOCK B), the bipolar NPN transistor (NPN1 or NPN4) in each block is used as a driver for reading operations of the data stored in the memory cells (P1 to P8 or N1 to N8) in each block (BLOCK A or BLOCK B), and the output line (OUTPUT LINE B or OUTPUT LINE D) is kept at a logic state "0" before reading operations for the memory cells (P1 to P8 or N1 to N8).
摘要翻译：公开了一种双极型CMOS门阵列型半导体集成电路，其具有多个排列成矩阵的基本单元（8,9,10和11），每个基本单元包括作为存储器的MOS晶体管（P1到P4和N1到N4）单元，双极晶体管（NPN1）和电阻（R1）以及用于将存储在存储单元中的数据传输到外部的位线，并且半导体集成电路的特征在于，基本单元（8,9,10和 11）被分组为多个块（块A和块B），每个块中的双极NPN晶体管（NPN1或NPN4）被用作用于读取存储在存储单元（P1至P8或（P1至P8或N1）的读操作之前，输出线（输出线B或输出线D）保持在逻辑状态“0”，在每个块（块A或块B）到N8）。

3. 发明公开

EP0336741A2 Semiconductor integrated circuit with bipolar transistors and MOSFETs 失效
标题翻译： Integrierter Halbleiterschaltkreis mit Bipolartransistoren和MOSFETs。
公开(公告)号：EP0336741A2
公开(公告)日：1989-10-11
申请号：EP89303377.9
申请日：1989-04-05
申请人： HITACHI, LTD.
发明人： Miyaoka, Shuuichi , Odaka, Masanori , Ogiue, Katsumi
IPC分类号： H01L27/02 , H03K19/094
CPC分类号： H03K19/09448 , H01L27/11896
摘要： A logic circuit forming a gate array is designed depending upon the value of the output load capacitance thereof, from among a CMOS circuit, a first Bi-CMOS circuit including an output bipolar transistor whose emitter size is set at a predetermined value and a second Bi-CMOS circuit including an output bipolar transistor whose emitter size is larger than the emitter size of the output bipolar transistor of the first Bi-CMOS circuit. In this way, the logic circuit is brought into a circuit form whose output load capacitance can be charged and discharged fastest. As a result, the logic circuit constructed in the gate array by adopting the design technique as stated above has its operating speed raised.
摘要翻译：形成门阵列的逻辑电路根据其输出负载电容的值从CMOS电路，包括发射极尺寸设定在预定值的输出双极型晶体管的第一Bi-CMOS电路和第二Bi -CMOS电路包括输出双极晶体管，其发射极尺寸大于第一Bi-CMOS电路的输出双极晶体管的发射极尺寸。以这种方式，逻辑电路成为其输出负载电容可以最快充放电的电路形式。结果，通过采用如上所述的设计技术在门阵列中构成的逻辑电路具有提高其运行速度。

4. 发明公开

EP0329152A2 Semiconductor device with gate array 失效
标题翻译： Halbleiteranordnung mit Gattermatrix。
公开(公告)号：EP0329152A2
公开(公告)日：1989-08-23
申请号：EP89102755.9
申请日：1989-02-17
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hara, Hiroyuki , Sugimoto, Yasuhiro , Nagamatsu, Tetsu
IPC分类号： H01L27/06 , H03K19/082 , H03K19/094
CPC分类号： H03K19/09448 , H01L27/11896 , H03K19/1735
摘要： A semiconductor device is disclosed having a channeless gate array. A plurality of standard cells (11) are formed on a gate array chip such that one of the standard cells is formed relative to the adjacent standard cell with a bipolar transistor (21) and resistor (26) shared, as a BiCMOS logic gate, by the mutually adjacent standard cells at one end.
摘要翻译：公开了一种具有无通道门阵列的半导体器件。多个标准单元（11）形成在栅极阵列芯片上，使得标准单元之一相对于相邻的标准单元以双极晶体管（21）和电阻（26）形成，作为BiCMOS逻辑门，通过相邻的标准单元在一端。

5. 发明授权

EP0133131B1 Master slice IC device 失效
标题翻译：主芯片设备
公开(公告)号：EP0133131B1
公开(公告)日：1989-01-04
申请号：EP84401568.5
申请日：1984-07-26
申请人： FUJITSU LIMITED
发明人： Tanizawa, Tetsu
IPC分类号： H01L27/02
CPC分类号： H01L21/82 , H01L27/11896

6. 发明公开

EP0133131A3 Master slice IC device 失效
标题翻译：主芯片设备
公开(公告)号：EP0133131A3
公开(公告)日：1986-01-22
申请号：EP84401568
申请日：1984-07-26
申请人： FUJITSU LIMITED
发明人： Tanizawa, Tetsu
IPC分类号： H01L27/02
CPC分类号： H01L21/82 , H01L27/11896
摘要： A master slice IC device comprising at least two kind of basic cells (6,8); that is, a first kind of basic cells (6) each having one or more n-type MIS transistors (Q2) and one or more p-type MIS transistors (01) to form a CMIS logic circuit, and a second kind of basic cells (8) each comprising an npn-type bipolar transistor (Q3) and a pnp-type bipolar transistor (Q4) to form a bipolar buffer circuit having a large drive ability, The second kind of basic cells (8) are used, for example, only when the fan-out number is large and/or the length of the connection lines is long, thereby realizing a high degree of freedom in circuit design and a high operating speed without increasing the power consumption.

7. 发明授权

EP0528956B1 BASIC CELL FOR BiCMOS GATE ARRAY 失效
标题翻译：依据CELL BICMOS栅场
公开(公告)号：EP0528956B1
公开(公告)日：1999-06-30
申请号：EP91910089.1
申请日：1991-05-08
申请人： Synopsys, Inc.
发明人： EL GAMAL, Abbas
IPC分类号： H03K19/01 , H03K19/003 , H03K19/082 , H03K19/094 , H03K19/0944 , H03K19/173 , H01L27/118
CPC分类号： H03K19/09448 , H01L27/11896 , H03K19/1735

8. 发明公开

EP0735587A2 BiMOS integrated circuit 失效
标题翻译： Integrierte BiMOS-Schaltungen
公开(公告)号：EP0735587A2
公开(公告)日：1996-10-02
申请号：EP96105052.3
申请日：1996-03-29
申请人： NEC CORPORATION
发明人： Okamura, Hitoshi
IPC分类号： H01L27/118
CPC分类号： H01L27/11896
摘要： Disclosed is a BiMOS integrated circuit, which has: a bipolar transistor for output pull-up; a BiMOS hybrid gate buffer section which comprises a MOS transistor for output pull-down which is longitudinally connected to the bipolar transistor, and a MOS transistor for base drive which comprises an output which is connected a base of the bipolar transistor to drive the base and a gate which is connected to an input; and a logical section which comprises at least a CMOS gate, the logical section having an output which is connected to the input; wherein the base drive MOS transistor has an input capacitance less than that of the output pull-down MOS transistor.
摘要翻译：公开了一种BiMOS集成电路，其具有：用于输出上拉的双极晶体管; BiMOS混合栅极缓冲器部分，其包括纵向连接到双极晶体管的用于输出下拉的MOS晶体管，以及用于基极驱动的MOS晶体管，其包括连接到双极晶体管的基极以驱动基极的输出，以及连接到输入的门; 以及包括至少CMOS门极的逻辑部分，所述逻辑部分具有连接到所述输入端的输出端; 其中所述基极驱动MOS晶体管的输入电容小于所述输出下拉MOS晶体管的输入电容。

9. 发明公开

EP0528956A4 EP0528956A4 - 失效
标题翻译： EP0528956A4 - Google专利
公开(公告)号：EP0528956A4
公开(公告)日：1994-01-05
申请号：EP91910089
申请日：1991-05-08
申请人： SIARC
发明人： EL GAMAL, ABBAS
IPC分类号： H01L21/82 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L27/118 , H03K3/356 , H03K19/08 , H03K19/0944 , H03K19/173 , H03K19/177 , H03K19/01
CPC分类号： H03K19/09448 , H01L27/11896 , H03K19/1735

10. 发明公开

EP0457150A3 BICMOS compacted logic array 失效
标题翻译： BICMOS压缩逻辑阵列
公开(公告)号：EP0457150A3
公开(公告)日：1992-06-17
申请号：EP91107314.6
申请日：1991-05-06
申请人： LSI LOGIC CORPORATION
发明人： Wong, Anthony Y. , Tam, Anna , Wong, Daniel
IPC分类号： H01L27/118 , H01L27/02
CPC分类号： H01L27/11896
摘要： A repeating cell structure in a semiconductor substrate for a BiCMOS logic gate array. The cell structure has three regions shaped as columns. The first columnar region is a P-well and has four vertically aligned active areas of N-type material formed within the columnar region. Each of the active areas has two gate electrodes to form two NMOS transistors. Similarly the second columnar region is a N-well and has four vertically aligned active areas of P-type material. Each such active region forms two PMOS transistors. The third column has two bipolar transistors, each with collector, base and emitter regions vertically aligned. The resulting BiCMOS logic array permits a flexible location of macrocells, which results in a compact implementation of the resulting integrated circuit.

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