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1. 发明授权

US06255158B1 Process of manufacturing a vertical dynamic random access memory device 失效
标题翻译：制造垂直动态随机存取存储器件的过程
公开(公告)号：US06255158B1
公开(公告)日：2001-07-03
申请号：US09667652
申请日：2000-09-22
申请人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
发明人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffision region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.
摘要翻译：动态随机存取存储器（DRAM）设备。 DRAM器件形成在具有顶表面的衬底和具有形成在衬底中的侧壁的沟槽中。使用沟槽的底部形成信号存储节点，并且使用沟槽的上部形成信号传送装置。信号传送装置包括耦合到信号存储节点并且从沟槽的侧壁延伸到衬底中的第一扩散区域，形成在衬底中邻近衬底的顶表面并邻近沟槽的侧壁的第二扩散区域，在所述第一扩散区域和所述第二扩散区域之间沿着所述沟槽的侧壁延伸的沟道区域，沿着从所述第一扩散区域延伸到所述第二扩散区域的所述沟槽的侧壁形成的栅极绝缘体，填充所述沟槽的栅极导体，具有顶表面，并且字线具有邻近栅极导体的顶表面的底部和与沟槽的侧壁对准的一侧。

2. 发明授权

US6153902A Vertical DRAM cell with wordline self-aligned to storage trench 有权
标题翻译：垂直DRAM单元与字线自对准到存储沟槽
公开(公告)号：US6153902A
公开(公告)日：2000-11-28
申请号：US374687
申请日：1999-08-16
申请人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
发明人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
IPC分类号： H01L27/108 , H01L21/8242 , H01L29/78 , H01L33/00
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate, a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffusion region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.
摘要翻译：动态随机存取存储器（DRAM）设备。 DRAM器件形成在具有顶表面的衬底和具有形成在衬底中的侧壁的沟槽中。使用沟槽的底部形成信号存储节点，并且使用沟槽的上部形成信号传送装置。信号传送装置包括耦合到信号存储节点并从沟槽的侧壁延伸到衬底中的第一扩散区域，形成在衬底中邻近衬底的顶表面并邻近沟槽的侧壁的第二扩散区域沿着沟槽的侧壁在第一扩散区域和第二扩散区域之间延伸的沟道区域，沿着从第一扩散区域延伸到第二扩散区域的沟槽的侧壁形成的栅极绝缘体，填充沟槽的栅极导体并且具有顶表面和字线，其具有邻近栅极导体的顶表面的底部和与沟槽的侧壁对准的一侧。

3. 发明授权

US06320215B1 Crystal-axis-aligned vertical side wall device 有权
标题翻译：水晶轴对齐垂直侧壁装置
公开(公告)号：US06320215B1
公开(公告)日：2001-11-20
申请号：US09359292
申请日：1999-07-22
申请人： Gary Bronner , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
发明人： Gary Bronner , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/1087 , H01L27/10876
摘要： A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.
摘要翻译：一种动态随机存取存储器（DRAM）单元，其包括具有部分地设置在沟槽的侧壁上的有源晶体管器件的深沟槽存储电容器。侧壁与具有沿着单晶轴的结晶取向的第一结晶平面对准。制造这种DRAM单元的方法包括：（a）在衬底中形成深沟槽，（b）沿着具有单晶取向的沟槽侧壁形成刻面晶体区域，以及（c）形成部分设置的晶体管器件在侧壁上的刻面晶体区域上。小面晶体区域可以通过生长氧化物环形成，例如通过局部热氧化在选择的氧化条件下，以促进沿着第一晶体轴系的较高的氧化速率而不是第二晶体轴系。

4. 发明授权

US06437388B1 Compact trench capacitor memory cell with body contact 失效
标题翻译：紧凑型沟槽电容器记忆体与身体接触
公开(公告)号：US06437388B1
公开(公告)日：2002-08-20
申请号：US09866278
申请日：2001-05-25
申请人： Carl J. Radens , Ulrike Gruening , Jack A. Mandelman
发明人： Carl J. Radens , Ulrike Gruening , Jack A. Mandelman
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/0218 , H01L27/10841 , H01L27/10876 , H01L27/10888 , H01L29/945
摘要： A semiconductor device includes at least two active areas, each active area surrounding a corresponding trench in a substrate. The trenches each include a capacitor in a lower portion of the trench and a gate in an upper portion of the trench. A vertical transistor is formed adjacent to the trench in the upper portion for charging and discharging the capacitor. A body contact is formed between the at least two active areas. The body contact connects to the at least two active areas and to a diffusion well of the substrate for preventing floating body effects in the vertical transistor.
摘要翻译：半导体器件包括至少两个有效区域，每个有源区域围绕衬底中相应的沟槽。沟槽中的每一个都包括位于沟槽下部的电容器和沟槽上部的栅极。在上部的沟槽附近形成垂直晶体管，用于对电容器进行充电和放电。在所述至少两个活动区域之间形成身体接触。身体接触件连接到至少两个有源区域和衬底的扩散阱，以防止垂直晶体管中的浮体效应。

5. 发明授权

US06630379B2 Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch 失效
标题翻译：制造具有垂直MOSFET和3F位线间距的6F2沟槽电容器DRAM单元的方法
公开(公告)号：US06630379B2
公开(公告)日：2003-10-07
申请号：US10011556
申请日：2001-11-06
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor extends down at least one side wall of the deep trench above the storage capacitor. The transistor has a source diffusion extending in the plane of the substrate adjacent the deep trench. An isolation extends down at least one other sidewall of the deep trench opposite the vertical transistor. Shallow trench isolation regions extend along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends. A gate conductor extends within the deep trench. A wordline extends over the deep trench and is connected to the gate conductor. A bitline extends above the surface plane of the substrate and has a contact to the source diffusion between the shallow trench isolation regions.
摘要翻译：一种存储单元结构，包括平面半导体衬底。深沟槽位于半导体衬底中。深沟槽具有多个侧壁和底部。存储电容器位于深沟槽的底部。垂直晶体管向下延伸存储电容器上方的深沟槽的至少一个侧壁。晶体管具有在邻近深沟槽的衬底的平面中延伸的源极扩散。隔离层向下延伸与垂直晶体管相对的深沟槽的至少另一侧壁。浅沟槽隔离区沿垂直晶体管延伸的横向于侧壁的方向沿着衬底的表面延伸。栅极导体在深沟槽内延伸。一条字线延伸穿过深沟槽并连接到栅极导体。位线延伸在衬底的表面平面之上，并且具有与浅沟槽隔离区之间的源极扩散的接触。

6. 发明授权

US06573137B1 Single sided buried strap 有权
标题翻译：单面埋地带
公开(公告)号：US06573137B1
公开(公告)日：2003-06-03
申请号：US09603442
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jack A. Mandelman , Wolfgang Bergner , Gary B. Bronner , Ulrike Gruening , Stephan Kudelka , Alexander Michaelis , Larry Nesbit , Carl J. Radens , Till Schloesser , Helmut Tews
发明人： Ramachandra Divakaruni , Jack A. Mandelman , Wolfgang Bergner , Gary B. Bronner , Ulrike Gruening , Stephan Kudelka , Alexander Michaelis , Larry Nesbit , Carl J. Radens , Till Schloesser , Helmut Tews
IPC分类号： H01L218242
CPC分类号： H01L27/10864
摘要： A method for clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A barrier material is deposited above a node conductor of the storage capacitor. A layer of silicon is deposited over the barrier material. Dopant ions are implanted at an angle into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.
摘要翻译：一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离环的方法，同时将隔离套环留在深沟槽的其它表面。屏蔽材料沉积在存储电容器的节点导体上方。一层硅沉积在阻挡材料上。掺杂离子以一定角度注入到深沟槽内沉积的硅层中，从而留下沉积的硅沿着深沟槽的一侧被植入。未投影的硅被蚀刻。隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

7. 发明授权

US06194755B1 Low-resistance salicide fill for trench capacitors 失效
标题翻译：沟槽电容器的低电阻自对准硅填料
公开(公告)号：US06194755B1
公开(公告)日：2001-02-27
申请号：US09102471
申请日：1998-06-22
申请人： Jeffrey P. Gambino , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
发明人： Jeffrey P. Gambino , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L2120
CPC分类号： H01L27/10861
摘要： Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide as a component of the trench electrode in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell layouts and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.
摘要翻译：使用导致难熔金属硅化物作为沟槽的下部区域中的沟槽电极的部件的方法来制造沟槽电容器。与具有类似尺寸的常规沟槽电极相比，含有自对接硅化物的沟槽电极显示出降低的串联电阻，从而可以减少接地规则存储单元布局和/或降低单元访问时间。本发明的沟槽电容器特别可用作DRAM存储单元的组件。

8. 发明授权

US06339241B1 Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch 有权
公开(公告)号：US06339241B1
公开(公告)日：2002-01-15
申请号：US09602426
申请日：2000-06-23
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor extends down at least one side wall of the deep trench above the storage capacitor. The transistor has a source diffusion extending in the plane of the substrate adjacent the deep trench. An isolation extends down at least one other sidewall of the deep trench opposite the vertical transistor. Shallow trench isolation regions extend along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends. A gate conductor extends within the deep trench. A wordline extends over the deep trench and is connected to the gate conductor. A bitline extends above the surface plane of the substrate and has a contact to the source diffusion between the shallow trench isolation regions.

9. 发明授权

US06451648B1 Process for buried-strap self-aligned to deep storage trench 失效
标题翻译：埋层自对准深沟槽工艺
公开(公告)号：US06451648B1
公开(公告)日：2002-09-17
申请号：US09233887
申请日：1999-01-20
申请人： Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
发明人： Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10861
摘要： A process for forming a buried strap self-aligned to a deep storage trench. Spacers are formed on walls of a recess over a filled deep trench capacitor and a substrate. A plug is formed in a region between the spacers. Photoresist is deposited over the spacers, the plug, and material surrounding the spacers of the plug. The photoresist is patterned, thereby exposing portions of the plug, the spacers, and the surrounding material. The spacers in the surrounding material not covered by the photoresist are selectively etched, leaving a remaining portion of the spacers. The substrate and the portion of the filled deep trench exposed by the spacer removal are selectively etched. An isolation region is formed in a space created by etching of the spacers, surrounding material, substrate, and filled deep trench.
摘要翻译：一种用于形成与深存储沟槽自对准的掩埋带的工艺。垫片形成在填充的深沟槽电容器和衬底上的凹部的壁上。插塞形成在间隔件之间的区域中。光刻胶沉积在隔离物，插塞和围绕插塞间隔物的材料上。对光致抗蚀剂进行图案化，从而暴露插头，间隔件和周围材料的部分。不被光致抗蚀剂覆盖的周围材料中的间隔物被选择性地蚀刻，留下间隔物的剩余部分。通过间隔物去除暴露的衬底和填充的深沟槽的部分被选择性地蚀刻。隔离区形成在通过蚀刻间隔物，周围的材料，衬底和填充的深沟槽而产生的空间中。

10. 发明授权

US06426251B2 Process for manufacturing a crystal axis-aligned vertical side wall device 失效
标题翻译：用于制造晶体轴对准的垂直侧壁装置的方法
公开(公告)号：US06426251B2
公开(公告)日：2002-07-30
申请号：US09894427
申请日：2001-06-28
申请人： Gary Bronner , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
发明人： Gary Bronner , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/1087 , H01L27/10876
摘要： A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.
摘要翻译：一种动态随机存取存储器（DRAM）单元，其包括具有部分地设置在沟槽的侧壁上的有源晶体管器件的深沟槽存储电容器。侧壁与具有沿着单晶轴的结晶取向的第一结晶平面对准。制造这种DRAM单元的方法包括：（a）在衬底中形成深沟槽，（b）沿着具有单晶取向的沟槽侧壁形成刻面晶体区域，以及（c）形成部分设置的晶体管器件在侧壁上的刻面晶体区域上。小面晶体区域可以通过生长氧化物环形成，例如通过局部热氧化在选择的氧化条件下，以促进沿着第一晶体轴系的较高的氧化速率而不是第二晶体轴系。

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