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1. 发明授权

US06573137B1 Single sided buried strap 有权
标题翻译：单面埋地带
公开(公告)号：US06573137B1
公开(公告)日：2003-06-03
申请号：US09603442
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jack A. Mandelman , Wolfgang Bergner , Gary B. Bronner , Ulrike Gruening , Stephan Kudelka , Alexander Michaelis , Larry Nesbit , Carl J. Radens , Till Schloesser , Helmut Tews
发明人： Ramachandra Divakaruni , Jack A. Mandelman , Wolfgang Bergner , Gary B. Bronner , Ulrike Gruening , Stephan Kudelka , Alexander Michaelis , Larry Nesbit , Carl J. Radens , Till Schloesser , Helmut Tews
IPC分类号： H01L218242
CPC分类号： H01L27/10864
摘要： A method for clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A barrier material is deposited above a node conductor of the storage capacitor. A layer of silicon is deposited over the barrier material. Dopant ions are implanted at an angle into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.
摘要翻译：一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离环的方法，同时将隔离套环留在深沟槽的其它表面。屏蔽材料沉积在存储电容器的节点导体上方。一层硅沉积在阻挡材料上。掺杂离子以一定角度注入到深沟槽内沉积的硅层中，从而留下沉积的硅沿着深沟槽的一侧被植入。未投影的硅被蚀刻。隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

2. 发明授权

US07738279B2 Integrated circuit and method of operating an integrated circuit 有权
标题翻译：集成电路和集成电路的操作方法
公开(公告)号：US07738279B2
公开(公告)日：2010-06-15
申请号：US12131802
申请日：2008-06-02
申请人： Stefan Slesazeck , Till Schloesser , Ulrike Gruening-Von Schwerin
发明人： Stefan Slesazeck , Till Schloesser , Ulrike Gruening-Von Schwerin
IPC分类号： G11C11/00
CPC分类号： G11C5/04 , G11C5/02 , G11C5/143 , G11C11/1673 , G11C13/0004 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C2013/0054 , G11C2213/71 , G11C2213/76 , G11C2213/79
摘要： According to one embodiment of the present invention, an integrated circuit is provided including a plurality of resistivity changing memory elements and a plurality of memory element select devices, wherein the select devices are floating body select devices.
摘要翻译：根据本发明的一个实施例，提供一种集成电路，其包括多个电阻率变化存储元件和多个存储元件选择器件，其中所述选择器件是浮动体选择器件。

3. 发明授权

US07539039B2 Integrated circuit having a resistive switching device 失效
标题翻译：具有电阻式开关装置的集成电路
公开(公告)号：US07539039B2
公开(公告)日：2009-05-26
申请号：US11694393
申请日：2007-03-30
申请人： Ulrike Gruening-von Schwerin , Till Schloesser
发明人： Ulrike Gruening-von Schwerin , Till Schloesser
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0004 , G11C2213/79
摘要： An integrated circuit, a memory cell, memory device and method of operating the memory device is disclosed. In one embodiment, an integrated circuit having a resistively switching memory cell includes a bitline electrode and a second electrode having a lower voltage potential than the bitline electrode; a switching active volume and a selection transistor connected in series between the bitline electrode and the second electrode. The second electrode is connected, via a connection transistor, to a third electrode having the same or a lower voltage potential than the second electrode; wherein the second electrode includes a buried electrode at least partially positioned below the bitline electrode and the third electrode.
摘要翻译：公开了一种集成电路，存储单元，存储器件和操作存储器件的方法。在一个实施例中，具有电阻切换存储单元的集成电路包括位线电极和具有比位线电极低的电压电位的第二电极; 开关有源体积和串联连接在位线电极和第二电极之间的选择晶体管。第二电极通过连接晶体管连接到具有与第二电极相同或更低电压电位的第三电极; 其中所述第二电极包括至少部分地位于所述位线电极和所述第三电极下方的掩埋电极。

4. 发明申请

US20080205118A1 INTEGRATED CIRCUIT HAVING A RESISTIVE SWITCHING DEVICE 失效
标题翻译：具有电阻开关器件的集成电路
公开(公告)号：US20080205118A1
公开(公告)日：2008-08-28
申请号：US11694393
申请日：2007-03-30
申请人： Ulrike Gruening-von Schwerin , Till Schloesser
发明人： Ulrike Gruening-von Schwerin , Till Schloesser
IPC分类号： G11C11/00 , H01L21/336
CPC分类号： G11C13/0011 , G11C13/0004 , G11C2213/79
摘要： An integrated circuit, a memory cell, memory device and method of operating the memory device is disclosed. In one embodiment, an integrated circuit having a resistively switching memory cell includes a bitline electrode and a second electrode having a lower voltage potential than the bitline electrode; a switching active volume and a selection transistor connected in series between the bitline electrode and the second electrode. The second electrode is connected, via a connection transistor, to a third electrode having the same or a lower voltage potential than the second electrode; wherein the second electrode includes a buried electrode at least partially positioned below the bitline electrode and the third electrode.
摘要翻译：公开了一种集成电路，存储单元，存储器件和操作存储器件的方法。在一个实施例中，具有电阻切换存储单元的集成电路包括位线电极和具有比位线电极低的电压电位的第二电极; 开关有源体积和串联连接在位线电极和第二电极之间的选择晶体管。第二电极通过连接晶体管连接到具有与第二电极相同或更低电压电位的第三电极; 其中所述第二电极包括至少部分地位于所述位线电极和所述第三电极下方的掩埋电极。

5. 发明申请

US20080217672A1 INTEGRATED CIRCUIT HAVING A MEMORY 审中-公开
标题翻译：具有存储器的集成电路
公开(公告)号：US20080217672A1
公开(公告)日：2008-09-11
申请号：US11684033
申请日：2007-03-09
申请人： Martin Popp , Ulrike Gruening-von Schwerin , Till Schloesser , Peter Lahnor , Rolf Weis , Odo Wunnicke
发明人： Martin Popp , Ulrike Gruening-von Schwerin , Till Schloesser , Peter Lahnor , Rolf Weis , Odo Wunnicke
IPC分类号： H01G4/40 , H01L21/62 , H01L27/01
CPC分类号： H01L27/10817 , H01G4/38 , H01G4/40 , H01L27/0207 , H01L27/10814 , H01L27/10852 , H01L27/10888 , H01L28/91
摘要： An integrated circuit having a memory arrangement including capacitor elements and further capacitor elements is disclosed. One embodiment provides a substrate layer with contact pads and further contact pads; the capacitor elements being disposed in a first level on the substrate layer and connected with the contact pads; the further capacitor elements being disposed in a second level above the first level; contact elements being disposed between the capacitor elements and connected with the further contact pads; the further capacitor elements being disposed above the contact elements and being connected with the contact elements.
摘要翻译：公开了具有包括电容器元件和其它电容器元件的存储器布置的集成电路。一个实施例提供具有接触垫和另外的接触垫的衬底层; 所述电容器元件设置在所述基底层上的第一层中并与所述接触垫相连接; 所述另外的电容器元件设置在高于所述第一电平的第二电平; 接触元件设置在电容器元件之间并与另外的接触垫连接; 另外的电容器元件设置在接触元件上方并与接触元件连接。

6. 发明授权

US07727837B2 Method of producing an integrated circuit having a capacitor with a supporting layer 失效
标题翻译：一种具有带支撑层的电容器的集成电路的制造方法
公开(公告)号：US07727837B2
公开(公告)日：2010-06-01
申请号：US11669613
申请日：2007-01-31
申请人： Ulrike Gruening-von Schwerin , Rolf Weis , Wolfgang Henke , Odo Wunnicke , Till Schloesser , Florian Schnabel , Wolfgang Mueller
发明人： Ulrike Gruening-von Schwerin , Rolf Weis , Wolfgang Henke , Odo Wunnicke , Till Schloesser , Florian Schnabel , Wolfgang Mueller
IPC分类号： H01L21/8242 , H01L21/20 , H01L21/302 , H01L21/461
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A method of forming an integrated circuit having a capacitor is disclosed. In one embodiment, the method includes forming a capacitor element with a first electrode, a dielectric layer and a second electrode. The capacitor element is formed using a support layer.
摘要翻译：公开了一种形成具有电容器的集成电路的方法。在一个实施例中，该方法包括形成具有第一电极，电介质层和第二电极的电容器元件。电容器元件使用支撑层形成。

7. 发明申请

US20080253160A1 INTEGRATED CIRCUIT HAVING A MEMORY CELL ARRAY AND METHOD OF FORMING AN INTEGRATED CIRCUIT 失效
标题翻译：具有存储单元阵列的集成电路和形成集成电路的方法
公开(公告)号：US20080253160A1
公开(公告)日：2008-10-16
申请号：US11735164
申请日：2007-04-13
申请人： Martin Popp , Till Schloesser , Ulrike Gruening-von Schwerin , Rolf Weis
发明人： Martin Popp , Till Schloesser , Ulrike Gruening-von Schwerin , Rolf Weis
IPC分类号： G11C5/06 , H01L21/82
CPC分类号： H01L27/10817 , G11C5/063 , H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75.
摘要翻译：公开了一种具有存储单元阵列的集成电路和形成集成电路的方法。一个实施例提供沿着第一方向行进的位线，沿着基本上垂直于第一方向的第二方向行进的字线，有效区域和位线接触。位线触点被布置成沿着第二方向延伸的列，并且以沿第一方向延伸的列布置。相邻位线之间的距离为DL，相邻位线触点之间的距离为DC，DC平行于第一方向测量。以下关系成立：1 / 2.25 <= DL / DC <= 1 / 1.75。

8. 发明申请

US20080099814A1 INTEGRATED CIRCUIT AND METHOD FOR PRODUCTION 审中-公开
标题翻译：集成电路和生产方法
公开(公告)号：US20080099814A1
公开(公告)日：2008-05-01
申请号：US11554335
申请日：2006-10-30
申请人： Ulrike Gruening-von Schwerin , Till Schloesser
发明人： Ulrike Gruening-von Schwerin , Till Schloesser
IPC分类号： H01L27/10 , H01L21/336 , H01L21/82
CPC分类号： H01L27/2454 , G11C13/0004 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： An array of vertical transistor cells formed in a substrate for selecting one of a plurality of memory cells by selecting a word line and a bit line is disclosed. In one embodiment, for minimizing the area of a cell and reducing complexity in production a plurality of parallel insulating trenches filled with an insulating material and a plurality of perpendicular gate electrode trenches is formed, the gate electrode trenches filled with a suitable gate electrode material disrupted by the insulating material thus forming separate gate electrodes arranged below the reference plane. The insulating trenches and the gate electrode trenches form distinct active areas of transistors in the substrate, wherein two gate electrodes located at opposing sidewalls of an active area form a double gate electrode of a transistor, and wherein a plurality of gate electrodes is coupled to a word line running perpendicular to the gate electrode trenches and above the reference plane.
摘要翻译：公开了通过选择字线和位线而形成在用于选择多个存储单元中的一个的基板中的垂直晶体管单元的阵列。在一个实施例中，为了最小化单元的面积并降低生产的复杂性，形成多个平行的绝缘沟槽，其填充有绝缘材料和多个垂直的栅极电极沟槽，栅电极沟槽填充有合适的栅电极材料中断由绝缘材料形成分开的栅极电极，布置在参考平面下方。绝缘沟槽和栅极电极沟槽在衬底中形成晶体管的不同有源区，其中位于有源区的相对侧壁处的两个栅电极形成晶体管的双栅电极，并且其中多个栅电极耦合到字线垂直于栅极电极沟槽并在参考平面上方延伸。

9. 发明授权

US07132333B2 Transistor, memory cell array and method of manufacturing a transistor 有权
公开(公告)号：US07132333B2
公开(公告)日：2006-11-07
申请号：US10939255
申请日：2004-09-10
申请人： Till Schloesser , Rolf Weis , Ulrike Gruening-Von Schwerin
发明人： Till Schloesser , Rolf Weis , Ulrike Gruening-Von Schwerin
IPC分类号： H01L21/336
CPC分类号： G11C11/404 , H01L27/0207 , H01L27/10873 , H01L27/10879 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7854
摘要： A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, and a gate electrode disposed along said channel region and being electrically isolated from said channel region, for controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.

10. 发明授权

US07642572B2 Integrated circuit having a memory cell array and method of forming an integrated circuit 失效
标题翻译：具有存储单元阵列的集成电路和形成集成电路的方法
公开(公告)号：US07642572B2
公开(公告)日：2010-01-05
申请号：US11735164
申请日：2007-04-13
申请人： Martin Popp , Till Schloesser , Ulrike Gruening-von Schwerin , Rolf Weis
发明人： Martin Popp , Till Schloesser , Ulrike Gruening-von Schwerin , Rolf Weis
IPC分类号： H01L27/108
CPC分类号： H01L27/10817 , G11C5/063 , H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75.
摘要翻译：公开了一种具有存储单元阵列的集成电路和形成集成电路的方法。一个实施例提供沿着第一方向行进的位线，沿着基本上垂直于第一方向的第二方向行进的字线，有效区域和位线接触。位线触点被布置成沿着第二方向延伸的列，并且以沿第一方向延伸的列布置。相邻位线之间的距离为DL，相邻位线触点之间的距离为DC，DC平行于第一方向测量。以下关系成立：1 / 2.25 <= DL / DC <= 1 / 1.75。

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