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1. 发明授权

US07906390B2 Thin gate electrode CMOS devices and methods of fabricating same 有权
标题翻译：薄栅极CMOS器件及其制造方法
公开(公告)号：US07906390B2
公开(公告)日：2011-03-15
申请号：US11780519
申请日：2007-07-20
申请人： Jack A. Mandelman , William Robert Tonti
发明人： Jack A. Mandelman , William Robert Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L29/66545 , H01L21/28194 , H01L29/4958 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/6659
摘要： A CMOS device and method of forming the CMOS device. The device including a source and a drain formed in a semiconductor substrate, the source and the drain and separated by a channel region of the substrate; a gate dielectric formed on a top surface of the substrate and a very thin metal or metal alloy gate electrode formed on a top surface of the gate dielectric layer, a polysilicon line abutting and in electrical contact with the gate electrode, the polysilicon line thicker than the gate electrode. The method including, forming the gate electrode by forming a trench above the channel region and depositing metal into the trench.
摘要翻译：一种CMOS器件及其形成方法。所述器件包括形成在半导体衬底中的源极和漏极，所述源极和漏极由衬底的沟道区分隔开; 形成在基板的顶表面上的栅极电介质和形成在栅极电介质层的顶表面上的非常薄的金属或金属合金栅电极，与栅电极邻接并与之电接触的多晶硅线，多晶硅线比栅电极。该方法包括：通过在沟道区域上方形成沟槽并将金属沉积到沟槽中形成栅电极。

2. 发明授权

US07785959B2 Method of multi-port memory fabrication with parallel connected trench capacitors in a cell 失效
标题翻译：在单元中并联连接沟槽电容器的多端口存储器制造方法
公开(公告)号：US07785959B2
公开(公告)日：2010-08-31
申请号：US12316748
申请日：2008-12-16
申请人： Kangguo Cheng , Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.
摘要翻译：提供了一种用于制造其中多个并联电容器在单元中的多端口存储器的方法。形成多个沟槽电容器，其具有沿多个沟槽的壁延伸的电容器电介质层，所述多个沟槽电容器具有第一电容器板和与第一电容器板相对的电容器电介质层的第二电容器板。第一电容器板导电地连接在一起，并且第二电容器板被导电地连接在一起。以这种方式，第一电容器板适于接收相同的可变电压，并且第二电容器板适于接收相同的固定电压。

3. 发明授权

US07784009B2 Electrically programmable π-shaped fuse structures and design process therefore 失效
标题翻译：因此电气可编程和形状的熔断器结构和设计过程
公开(公告)号：US07784009B2
公开(公告)日：2010-08-24
申请号：US11923833
申请日：2007-10-25
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
IPC分类号： G06F17/50
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuses for an integrated circuit and design structures thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void. The design structure for the fuse is embodied in a machine-readable medium for designing, manufacturing or testing a design of the fuse.
摘要翻译：提出了用于集成电路的电可编程保险丝及其设计结构，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和在第二支撑件上方的第二端子部分。保险丝，第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个“形”结构。第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙之上。保险丝的设计结构体现在用于设计，制造或测试保险丝设计的机器可读介质中。

4. 发明授权

US07777296B2 Nano-fuse structural arrangements having blow protection barrier spaced from and surrounding fuse link 失效
标题翻译：纳米熔丝结构布置具有隔离和围绕熔断体的防风保护栅
公开(公告)号：US07777296B2
公开(公告)日：2010-08-17
申请号：US11566865
申请日：2006-12-05
申请人： Haining S. Yang , Jack A. Mandelman
发明人： Haining S. Yang , Jack A. Mandelman
IPC分类号： H01L23/525
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/28525 , H01L21/76805 , H01L21/7682 , H01L21/76876 , H01L21/76879 , H01L23/5256 , H01L29/0673 , H01L29/0676 , H01L2221/1063 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： A nano-fuse structural arrangement, includes, for example, a semiconductor substrate having an electrically conductive region formed thereon; an electrically conductive elongated nano-structure having a maximum diameter of less than approximately 50 nm and a maximum length of approximately 250 nm and being formed on the electrically conductive region; a barrier having barrier parts completely spaced from and completely surrounding elongated outer surfaces of the nano-structure, the spaces between the barrier and surfaces consisting essentially of a vacuum and being approximately equally spaced, so that the electrically conductive elongated nano-structure is blowable responsive to an electrical current flowable there through in a range of approximately 4 μA to approximately 120 μA.
摘要翻译：纳米熔丝结构布置包括例如其上形成有导电区域的半导体衬底; 导电细长纳米结构，其具有小于约50nm的最大直径和约250nm的最大长度，并且形成在导电区域上; 阻挡层具有与纳米结构的细长外表面完全间隔开并且完全包围细长外表面的阻挡部分，阻挡层和表面之间的空间基本上由真空构成，并且大致等间隔，使得导电细长纳米结构是可发射的到大约4μA至大约120μA的范围内可流过的电流。

5. 发明授权

US07772649B2 SOI field effect transistor with a back gate for modulating a floating body 失效
标题翻译：具有用于调制浮体的背栅的SOI场效应晶体管
公开(公告)号：US07772649B2
公开(公告)日：2010-08-10
申请号：US12036325
申请日：2008-02-25
申请人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , Carl Radens , William Tonti
发明人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , Carl Radens , William Tonti
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66772 , H01L29/78612 , H01L29/78648
摘要： A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.
摘要翻译：将掩模层施加在顶部半导体层上并且被图案化以在开口中暴露浅沟槽隔离结构以及要在其中形成第一源极/漏极区域和主体的顶部半导体区域的一部分。将离子注入到开口区域内的埋入绝缘体层的一部分中以形成损坏的埋层绝缘体区域。去除浅沟槽隔离结构，并且损坏的埋层绝缘体区域被选择性地蚀刻到未损坏的埋入绝缘体部分以形成空腔。在顶部半导体区域的侧壁和暴露的底表面上形成介电层，并且形成填充空腔的背栅。形成接触以向后栅极提供电偏压，使得主体和第一源极/漏极区域的电势被电调制。

6. 发明授权

US07700466B2 Tunneling effect transistor with self-aligned gate 有权
标题翻译：具有自对准栅极的隧道效应晶体管
公开(公告)号：US07700466B2
公开(公告)日：2010-04-20
申请号：US11828740
申请日：2007-07-26
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman
IPC分类号： H01L21/425 , H01L21/76 , H01L21/20 , H01L21/36 , H01L21/3205 , H01L21/4763 , H01L21/302 , H01L21/461
CPC分类号： H01L29/7391 , H01L23/485 , H01L29/66356 , Y10S438/926 , Y10S438/979
摘要： In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor.
摘要翻译：在一个实施例中，可以使用心轴和外部虚拟间隔件来形成第一导电类型区域。去除心轴以形成其中形成第二导电类型区域的凹陷区域。在另一个实施例中，心轴从浅沟槽隔离中移除以形成凹陷区域，其中形成内部虚拟间隔物。第一导电类型区域和第二导电区域形成在凹陷区域的其余部分内。进行退火，使得第一导电类型区域和第二导电类型区域通过扩散彼此邻接。栅电极形成为与第一和第二导电区域之间的p-n结自对准。由栅电极控制的可能是亚光刻的p-n结构成本发明的隧道效应晶体管。

7. 发明申请

US20090115448A1 Design Structure for an Automatic Driver/Transmission Line/Receiver Impedance Matching Circuitry 失效
标题翻译：自动驱动器/传输线/接收机阻抗匹配电路的设计结构
公开(公告)号：US20090115448A1
公开(公告)日：2009-05-07
申请号：US11934825
申请日：2007-11-05
申请人： Wagdi W. Abadeer , Louis Lu-Chen Hsu , Jack A. Mandelman
发明人： Wagdi W. Abadeer , Louis Lu-Chen Hsu , Jack A. Mandelman
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03J3/185 , H03L7/08 , H03L7/0805 , H03L7/0891
摘要： A design structure for an impedance matcher that automatically matches impedance between a driver and a receiver. The design structure for an impedance matcher includes a phase-locked loop (PLL) circuit that locks onto a data signal provided by the driver. The impedance matcher also includes tunable impedance matching circuitry responsive to one or more voltage-controlled oscillator control signals within the PLL circuit so as to generate an output signal that is impedance matched with the receiver.
摘要翻译：用于阻抗匹配器的设计结构，其自动匹配驱动器和接收器之间的阻抗。阻抗匹配器的设计结构包括锁定到由驱动器提供的数据信号的锁相环（PLL）电路。阻抗匹配器还包括响应于PLL电路内的一个或多个压控振荡器控制信号的可调阻抗匹配电路，以产生与接收器阻抗匹配的输出信号。

8. 发明授权

US07521776B2 Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers 有权
标题翻译：使用掩埋复合中心的具有混合晶体取向的衬底上的CMOS电路的软误差降低
公开(公告)号：US07521776B2
公开(公告)日：2009-04-21
申请号：US11618346
申请日：2006-12-29
申请人： Ethan H. Cannon , Toshiharu Furukawa , Charles Koburger, III , Jack A. Mandelman , William Tonti
发明人： Ethan H. Cannon , Toshiharu Furukawa , Charles Koburger, III , Jack A. Mandelman , William Tonti
IPC分类号： H01L29/04
CPC分类号： H01L27/1203 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L29/1083
摘要： Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.
摘要翻译：公开了新的半导体结构和方法，用于通过在至少一个复合中心产生元件上植入至少一个复合中心产生元件以减少上述CMOS器件中的单一事件镦粗率来在混合取向技术的本体部分之下形成掩埋复合层。由复合中心产生元件引起的掩埋复合层中的晶体缺陷即使在高温退火之后也不会愈合，并且用作通过电离辐射产生的空穴和电子的复合中心。可以形成多个掩埋复合层。可选地，一个这样的层可以被正电压偏置以通过收集电子来阻止闭锁。

9. 发明授权

US07514323B2 Vertical SOI trench SONOS cell 有权
标题翻译：垂直SOI沟槽SONOS单元
公开(公告)号：US07514323B2
公开(公告)日：2009-04-07
申请号：US11164513
申请日：2005-11-28
申请人： David M. Dobuzinsky , Herbert L. Ho , Jack A. Mandelman , Yoichi Otani
发明人： David M. Dobuzinsky , Herbert L. Ho , Jack A. Mandelman , Yoichi Otani
IPC分类号： H01L29/00
CPC分类号： H01L29/792 , H01L21/26586 , H01L27/115 , H01L27/11568 , H01L29/7926
摘要： A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.
摘要翻译：提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元，其允许将致密的非易失性随机存取基于SOI的互补金属氧化物半导体（CMOS）技术的存储器（NVRAM）单元。使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

10. 发明申请

US20090072290A1 SOI CMOS COMPATIBLE MULTIPLANAR CAPACITOR 有权
标题翻译： SOI CMOS兼容多元电容器
公开(公告)号：US20090072290A1
公开(公告)日：2009-03-19
申请号：US11857770
申请日：2007-09-19
申请人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , William Tonti
发明人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , William Tonti
IPC分类号： H01L21/70 , H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/10861 , H01L28/60
摘要： An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.
摘要翻译：孤立的浅沟槽隔离部分形成在绝缘体上半导体衬底的顶部半导体部分以及浅沟槽隔离结构中。环形形状的沟槽形成在掺杂顶部半导体部分周围，并填充有诸如掺杂多晶硅的导电材料。隔离的浅沟槽隔离部分和由导电材料的环限定的掩埋绝缘体层的部分被蚀刻以形成空腔。在空腔内的暴露的半导体表面上和掺杂的顶部半导体部分之上形成电容器电介质。形成在沟槽中并且在掺杂顶部半导体部分上方的导电材料部分构成电容器的内部电极，而导电材料的环，掺杂的顶部半导体部分和与电容器电介质邻接的手柄衬底的一部分构成一个第二电极。

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