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    • 3. 发明授权
    • Electrically programmable π-shaped fuse structures and design process therefore
    • 因此电气可编程和形状的熔断器结构和设计过程
    • US07784009B2
    • 2010-08-24
    • US11923833
    • 2007-10-25
    • Roger A. Booth, Jr.Kangguo ChengJack A. MandelmanWilliam R. Tonti
    • Roger A. Booth, Jr.Kangguo ChengJack A. MandelmanWilliam R. Tonti
    • G06F17/50
    • H01L23/5256H01L2924/0002H01L2924/00
    • Electrically programmable fuses for an integrated circuit and design structures thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void. The design structure for the fuse is embodied in a machine-readable medium for designing, manufacturing or testing a design of the fuse.
    • 提出了用于集成电路的电可编程保险丝及其设计结构,其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上,第一支撑件和第二支撑件间隔开,并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和 在第二支撑件上方的第二端子部分。 保险丝,第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个“形”结构。 第一端子部分,第二端子部分和熔丝元件是共面的,其中熔丝元件位于空隙之上。 保险丝的设计结构体现在用于设计,制造或测试保险丝设计的机器可读介质中。
    • 10. 发明申请
    • SOI CMOS COMPATIBLE MULTIPLANAR CAPACITOR
    • SOI CMOS兼容多元电容器
    • US20090072290A1
    • 2009-03-19
    • US11857770
    • 2007-09-19
    • Kangguo ChengLouis C. HsuJack A. MandelmanWilliam Tonti
    • Kangguo ChengLouis C. HsuJack A. MandelmanWilliam Tonti
    • H01L21/70H01L27/108
    • H01L27/1203H01L21/84H01L27/0629H01L27/10861H01L28/60
    • An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.
    • 孤立的浅沟槽隔离部分形成在绝缘体上半导体衬底的顶部半导体部分以及浅沟槽隔离结构中。 环形形状的沟槽形成在掺杂顶部半导体部分周围,并填充有诸如掺杂多晶硅的导电材料。 隔离的浅沟槽隔离部分和由导电材料的环限定的掩​​埋绝缘体层的部分被蚀刻以形成空腔。 在空腔内的暴露的半导体表面上和掺杂的顶部半导体部分之上形成电容器电介质。 形成在沟槽中并且在掺杂顶部半导体部分上方的导电材料部分构成电容器的内部电极,而导电材料的环,掺杂的顶部半导体部分和与电容器电介质邻接的手柄衬底的一部分构成一个 第二电极。