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1. 发明授权

US6153902A Vertical DRAM cell with wordline self-aligned to storage trench 有权
标题翻译：垂直DRAM单元与字线自对准到存储沟槽
公开(公告)号：US6153902A
公开(公告)日：2000-11-28
申请号：US374687
申请日：1999-08-16
申请人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
发明人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
IPC分类号： H01L27/108 , H01L21/8242 , H01L29/78 , H01L33/00
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate, a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffusion region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.
摘要翻译：动态随机存取存储器（DRAM）设备。 DRAM器件形成在具有顶表面的衬底和具有形成在衬底中的侧壁的沟槽中。使用沟槽的底部形成信号存储节点，并且使用沟槽的上部形成信号传送装置。信号传送装置包括耦合到信号存储节点并从沟槽的侧壁延伸到衬底中的第一扩散区域，形成在衬底中邻近衬底的顶表面并邻近沟槽的侧壁的第二扩散区域沿着沟槽的侧壁在第一扩散区域和第二扩散区域之间延伸的沟道区域，沿着从第一扩散区域延伸到第二扩散区域的沟槽的侧壁形成的栅极绝缘体，填充沟槽的栅极导体并且具有顶表面和字线，其具有邻近栅极导体的顶表面的底部和与沟槽的侧壁对准的一侧。

2. 发明授权

US06255158B1 Process of manufacturing a vertical dynamic random access memory device 失效
标题翻译：制造垂直动态随机存取存储器件的过程
公开(公告)号：US06255158B1
公开(公告)日：2001-07-03
申请号：US09667652
申请日：2000-09-22
申请人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
发明人： Toshiharu Furukawa , Ulrike Gruening , David V. Horak , Jack A. Mandelman , Carl J. Radens , Thomas S. Rupp
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffision region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.
摘要翻译：动态随机存取存储器（DRAM）设备。 DRAM器件形成在具有顶表面的衬底和具有形成在衬底中的侧壁的沟槽中。使用沟槽的底部形成信号存储节点，并且使用沟槽的上部形成信号传送装置。信号传送装置包括耦合到信号存储节点并且从沟槽的侧壁延伸到衬底中的第一扩散区域，形成在衬底中邻近衬底的顶表面并邻近沟槽的侧壁的第二扩散区域，在所述第一扩散区域和所述第二扩散区域之间沿着所述沟槽的侧壁延伸的沟道区域，沿着从所述第一扩散区域延伸到所述第二扩散区域的所述沟槽的侧壁形成的栅极绝缘体，填充所述沟槽的栅极导体，具有顶表面，并且字线具有邻近栅极导体的顶表面的底部和与沟槽的侧壁对准的一侧。

3. 发明授权

US06380027B2 Dual tox trench dram structures and process using V-groove 失效
标题翻译：双毒tox沟结构和工艺采用V型槽
公开(公告)号：US06380027B2
公开(公告)日：2002-04-30
申请号：US09225127
申请日：1999-01-04
申请人： Toshiharu Furukawa , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl J. Radens , William R. Tonti , Mary E. Weybright
发明人： Toshiharu Furukawa , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl J. Radens , William R. Tonti , Mary E. Weybright
IPC分类号： H01L21242
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10829 , H01L27/10894
摘要： A structure and method for simultaneously forming array structures and support structures on a substrate comprises forming the array structures to have a V-groove, forming the support structures to have a planar surface, and simultaneously forming a first oxide in the V-groove and a second oxide in the planar surface, wherein the first oxide is thicker than the second oxide.
摘要翻译：用于在衬底上同时形成阵列结构和支撑结构的结构和方法包括：形成阵列结构以具有V形槽，形成支撑结构以具有平坦表面，同时在V形槽中形成第一氧化物，以及其中所述第一氧化物比所述第二氧化物厚。

4. 发明授权

US6114725A Structure for folded architecture pillar memory cell 失效
标题翻译：折叠式立柱式记忆体的新型结构
公开(公告)号：US6114725A
公开(公告)日：2000-09-05
申请号：US93928
申请日：1998-06-09
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Howard L. Kalter , Jack A. Mandelman , Paul A. Rabidoux , Jeffrey J. Welser
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Howard L. Kalter , Jack A. Mandelman , Paul A. Rabidoux , Jeffrey J. Welser
IPC分类号： H01L21/8242 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94 , H01L31/113 , H01L31/119 , H01L31/62
CPC分类号： H01L27/11556 , H01L27/10808 , H01L27/10823 , H01L27/10841 , H01L27/10897 , H01L27/115
摘要： A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each cell. Two wordlines are formed per pillar on opposite pillar sidewalls which are along the row direction. The threshold voltage of the pillar device is raised on the side of the pillar touching the passing wordline, thereby permanently shutting off the pillar device during the cell operation and isolating the pillar from the voltage variations on the passing wordline. The isolated wordlines allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM application, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively.
摘要翻译：公开了一种具有支柱的紧密堆叠的垂直半导体器件阵列及其制造方法。该阵列具有字线和位线列。阵列具有垂直柱，每个具有两个字线，一个有效，另一个通过每个单元格。在沿着行方向的相对的支柱侧壁上的每个柱形成两个字线。支柱装置的阈值电压在柱体侧面升高，接触通过字线，从而在电池工作期间永久地关闭支柱装置，并将支柱与通过字线上的电压变化隔离。孤立的字线允许在易失性和非易失性存储单元配置中通过直接隧道寻址和写入各个单元。对于Gbit DRAM应用，可以在支柱上或在柱子周围的沟槽中分别形成堆叠或沟槽电容器。

5. 发明授权

US06333533B1 Trench storage DRAM cell with vertical three-sided transfer device 失效
标题翻译：沟槽存储DRAM单元，具有垂直三面传输设备
公开(公告)号：US06333533B1
公开(公告)日：2001-12-25
申请号：US09394964
申请日：1999-09-10
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky , Jack A. Mandelman
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876
摘要： A pair of dynamic random access memory cells having each end of the active area surrounded on three sides by a gate conductor. The width of each end of the active area that is surrounded by a gate conductor preferably is less than fifty percent of the width of the deep trench intersected by that end of the active area.
摘要翻译：一对动态随机存取存储器单元，其有源区域的每个端部由三个侧面由栅极导体包围。由栅极导体围绕的有源区域的每个端部的宽度优选地小于由有源区域的该端部相交的深沟槽的宽度的百分之五十。

6. 发明授权

US06207540B1 Method for manufacturing high performance MOSFET device with raised source and drain 失效
标题翻译：用于制造具有升高的源极和漏极的高性能MOSFET器件的方法
公开(公告)号：US06207540B1
公开(公告)日：2001-03-27
申请号：US09379940
申请日：1999-08-24
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma , Jack A. Mandelman
IPC分类号： H01L2138
CPC分类号： H01L29/66613 , H01L21/2255 , H01L29/66621 , H01L29/7834
摘要： A MOSFET device and a method of manufacturing the device. The device has a trench formed in a silicon substrate. The channel of the device is at the bottom of the trench. Diffusion layers are formed adjacent to opposite sides of the trench. Each diffusion layer is connected to the edge of the device channel by extending the diffusion layer along the side wall of the trench and under a portion of the trench.
摘要翻译：一种MOSFET器件及其制造方法。该器件具有形成在硅衬底中的沟槽。设备的通道位于沟槽的底部。扩散层邻近沟槽的相对侧形成。通过沿着沟槽的侧壁和沟槽的一部分延伸扩散层，将每个扩散层连接到器件沟道的边缘。

7. 发明授权

US6107133A Method for making a five square vertical DRAM cell 失效
标题翻译：制造五平方垂直DRAM单元的方法
公开(公告)号：US6107133A
公开(公告)日：2000-08-22
申请号：US85965
申请日：1998-05-28
申请人： Toshiharu Furukawa , Mark C. Hakey , David V. Horak , William H. Ma , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , David V. Horak , William H. Ma , Jack A. Mandelman
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10867
摘要： Five square dynamic random access memory (DRAM) cell is prepared with a vertical transfer device with long channel length. In this construction, channel length is not affected by cell size scaling requirements.
摘要翻译：使用具有长通道长度的垂直传送装置制备五平方动态随机存取存储器（DRAM）单元。在这种结构中，通道长度不受单元尺寸缩放要求的影响。

8. 发明授权

US07358120B2 Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROM 有权
标题翻译：绝缘体上硅（SOI）只读存储器（ROM）阵列和制造SOI ROM的方法
公开(公告)号：US07358120B2
公开(公告)日：2008-04-15
申请号：US11672251
申请日：2007-02-07
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Jack A. Mandelman
IPC分类号： H01L21/82
CPC分类号： H01L27/1203 , H01L27/1021 , H01L27/112 , H01L27/11213
摘要： A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface of the stripes. ROM cell personalization is the presence or absence of a diode and/or contact.
摘要翻译：绝缘体上硅（SOI）只读存储器（ROM）以及制造SOI ROM的方法。 ROM单元位于导体层上的表面SOI层中的条纹与正交取向的导线之间的交叉处。电线的触点连接到条纹上表面的ROM单元二极管。 ROM单元个性化是存在或不存在二极管和/或接触。

9. 发明授权

US06440801B1 Structure for folded architecture pillar memory cell 有权
标题翻译：折叠式立柱式记忆体结构
公开(公告)号：US06440801B1
公开(公告)日：2002-08-27
申请号：US09604901
申请日：2000-06-28
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Howard L. Kalter , Jack A. Mandelman , Paul A. Rabidoux , Jeffrey J. Welser
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Howard L. Kalter , Jack A. Mandelman , Paul A. Rabidoux , Jeffrey J. Welser
IPC分类号： H01L21336
CPC分类号： H01L27/11556 , H01L27/10808 , H01L27/10823 , H01L27/10841 , H01L27/10897 , H01L27/115
摘要： A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each, cell. Two wordlines are formed per pillar on opposite pillar sidewalls which are along the row direction. The threshold voltage of the pillar device is raised on the side of the pillar touching the passing wordline, thereby permanently shutting off the pillar device during the cell operation and isolating the pillar from the voltage variations on the passing wordline. The isolated wordlines allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM application, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively.
摘要翻译：公开了一种具有支柱的紧密堆叠的垂直半导体器件阵列及其制造方法。该阵列具有字线和位线列。阵列具有垂直柱，每个具有两个字线，一个有效，另一个通过每个单元格。在沿着行方向的相对的支柱侧壁上的每个柱形成两个字线。支柱装置的阈值电压在柱体侧面升高，接触通过字线，从而在电池工作期间永久地关闭支柱装置，并将支柱与通过字线上的电压变化隔离。孤立的字线允许在易失性和非易失性存储单元配置中通过直接隧道寻址和写入各个单元。对于Gbit DRAM应用，可以在支柱上或在柱子周围的沟槽中分别形成堆叠或沟槽电容器。

10. 发明授权

US06225158B1 Trench storage dynamic random access memory cell with vertical transfer device 失效
标题翻译：沟槽存储动态随机存取存储单元与垂直传输设备
公开(公告)号：US06225158B1
公开(公告)日：2001-05-01
申请号：US09086057
申请日：1998-05-28
申请人： Toshiharu Furukawa , Mark C. Hakey , David V. Horak , William H. Ma , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , David V. Horak , William H. Ma , Jack A. Mandelman
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10891
摘要： A trench storage dynamic random access memory cell with vertical transfer device can be formed in a wafer having prepared shallow trench isolation. Vertical transfer device is built as the deep trenches are formed. Using square printing to form shallow trench isolation and deep trenches, allows for scaling of the cell to very small dimensions.
摘要翻译：可以在具有准备的浅沟槽隔离的晶片中形成具有垂直传输装置的沟槽存储动态随机存取存储器单元。随着形成深沟而建立垂直传输装置。使用方形印刷形成浅沟槽隔离和深沟槽，允许将电池缩放到非常小的尺寸。

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