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1. 发明授权

US09054156B2 Non-lithographic hole pattern formation 有权
标题翻译：非平版孔图案形成
公开(公告)号：US09054156B2
公开(公告)日：2015-06-09
申请号：US13561133
申请日：2012-07-30
申请人： Chiahsun Tseng , David V. Horak , Chun-chen Yeh , Yunpeng Yin
发明人： Chiahsun Tseng , David V. Horak , Chun-chen Yeh , Yunpeng Yin
IPC分类号： H01L21/768 , H01L23/498
CPC分类号： H01L21/768 , H01L21/02244 , H01L21/02247 , H01L21/02249 , H01L21/02252 , H01L21/0332 , H01L21/0337 , H01L21/32139 , H01L21/76816 , H01L23/498 , H01L29/0692 , H01L45/1691 , H01L2924/0002 , H01L2924/00
摘要： A metal layer is deposited over a material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation or nitridation. A hard mask portion is formed over the metal layer. A plasma impermeable spacer is formed on at least one first sidewall of the hard mask portion, while at least one second sidewall of the hard mask portion is physically exposed. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. A sequence of a surface pull back of the hard mask portion, cavity etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a hole pattern having a spacing that is not limited by lithographic minimum dimensions.
摘要翻译：金属层沉积在材料层上。金属层包括可通过等离子体氧化或氮化转化为含介电金属的化合物的元素金属。在金属层上形成硬掩模部分。在硬掩模部分的至少一个第一侧壁上形成等离子体不可渗透的间隔物，同时硬掩模部分的至少一个第二侧壁物理暴露。进行等离子体氧化或氮化以将金属层的物理暴露表面转化为含介电金属的化合物。重复将硬掩模部分的表面拉回序列，腔蚀刻，另一表面拉回和将顶表面转化为含介电金属的化合物，以形成具有不受光刻最小值限制的间隔的孔图案尺寸。

2. 发明授权

US08946866B2 Microelectronic substrate having removable edge extension element 有权
标题翻译：具有可移除边缘延伸元件的微电子基板
公开(公告)号：US08946866B2
公开(公告)日：2015-02-03
申请号：US13490239
申请日：2012-06-06
申请人： Charles W. Koburger, III , Steven J. Holmes , David V. Horak , Kurt R. Kimmel , Karen E. Petrillo , Christopher F. Robinson
发明人： Charles W. Koburger, III , Steven J. Holmes , David V. Horak , Kurt R. Kimmel , Karen E. Petrillo , Christopher F. Robinson
IPC分类号： H01L29/06 , G03F7/20
CPC分类号： G03F7/70691 , G03F7/70341 , G03F7/70808
摘要： An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element extending laterally from the peripheral edge of the microelectronic substrate and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge.
摘要翻译：提供包括微电子衬底的制品作为在微电子衬底的处理期间可用的制品。这种物品包括具有前表面，与前表面相对的后表面和在前表面和后表面的边界处的周边边缘的微电子基底。前表面是物品的主要表面。具有前表面，后表面和在前表面和后表面之间延伸的内边缘的可拆卸的环形边缘延伸元件具有接合到微电子基板的周边边缘的内边缘。以这种方式，形成连续表面，其包括边缘延伸元件的前表面，该边缘延伸元件从微电子基底的周边边缘和微电子基底的前表面横向延伸，连续表面基本上共平面且平坦，周缘连接到内边缘。

3. 发明授权

US08853076B2 Self-aligned contacts 有权
标题翻译：自对准接触
公开(公告)号：US08853076B2
公开(公告)日：2014-10-07
申请号：US13607856
申请日：2012-09-10
申请人： Su Chen Fan , David V. Horak , Shom Ponoth , David L. Rath , Muthumanickam Sankarapandian
发明人： Su Chen Fan , David V. Horak , Shom Ponoth , David L. Rath , Muthumanickam Sankarapandian
IPC分类号： H01L21/44
CPC分类号： H01L21/28088 , H01L21/76897 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： Self-aligned contacts in a metal gate structure and methods of manufacture are disclosed herein. The method includes forming a metal gate structure having a sidewall structure. The method further includes recessing the metal gate structure and forming a masking material within the recess. The method further includes forming a borderless contact adjacent to the metal gate structure, overlapping the masking material and the sidewall structure.
摘要翻译：本文公开了金属栅极结构中的自对准触点和制造方法。该方法包括形成具有侧壁结构的金属栅极结构。该方法还包括使金属栅极结构凹陷并在凹槽内形成掩模材料。该方法还包括在金属栅极结构附近形成无边界接触，与掩模材料和侧壁结构重叠。

4. 发明授权

US08772168B2 Formation of the dielectric cap layer for a replacement gate structure 有权
标题翻译：用于替代栅极结构的电介质盖层的形成
公开(公告)号：US08772168B2
公开(公告)日：2014-07-08
申请号：US13353708
申请日：2012-01-19
申请人： Ruilong Xie , Balasubramanian Pranatharthi Haran , David V. Horak , Su Chen Fan
发明人： Ruilong Xie , Balasubramanian Pranatharthi Haran , David V. Horak , Su Chen Fan
IPC分类号： H01L21/311
CPC分类号： H01L29/42376 , H01L21/28088 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape.
摘要翻译：通过在更换的栅极结构中形成电介质盖来减少接触短路的栅极。实施例包括在衬底上形成替代的栅极结构，所述替换的栅极结构包括具有空腔的ILD，在ILD的顶表面上的第一金属和衬里的空腔，以及在第一金属上填充空腔的第二金属，平面化第一和第二金属，在第二金属上形成氧化物，去除氧化物，使空腔中的第一和第二金属凹陷，形成凹陷，并用电介质材料填充凹槽。实施例还包括具有垂直侧壁，梯形形状，T形或Y形的电介质盖。

5. 发明申请

US20140061930A1 OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE 有权
标题翻译：通过掩蔽和反应离子蚀刻（RIE）技术的超耐性
公开(公告)号：US20140061930A1
公开(公告)日：2014-03-06
申请号：US13604660
申请日：2012-09-06
申请人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/528 , H01L21/31144 , H01L21/76807 , H01L21/76816 , H01L21/76831 , H01L23/5226 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.
摘要翻译：提供了一种方法，其包括首先根据第一掩模蚀刻衬底。第一蚀刻在衬底中形成第一深度的第一蚀刻特征。第一蚀刻还在衬底中形成条条开口。然后可以用填充材料填充条子开口。可以通过去除第一掩模的一部分来形成第二掩模。可以用第二蚀刻蚀刻由第二掩模曝光的衬底，其中第二蚀刻对填充材料是选择性的。第二蚀刻将第一蚀刻特征延伸到大于第一深度的第二深度，并且第二蚀刻形成第二蚀刻特征。然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。

6. 发明申请

US20140027923A1 NON-LITHOGRAPHIC HOLE PATTERN FORMATION 有权
标题翻译：非平面孔型图形
公开(公告)号：US20140027923A1
公开(公告)日：2014-01-30
申请号：US13561133
申请日：2012-07-30
申请人： Chiahsun Tseng , David V. Horak , Chun-chen Yeh , Yunpeng Yin
发明人： Chiahsun Tseng , David V. Horak , Chun-chen Yeh , Yunpeng Yin
IPC分类号： H01L21/768 , H01L23/498
CPC分类号： H01L21/768 , H01L21/02244 , H01L21/02247 , H01L21/02249 , H01L21/02252 , H01L21/0332 , H01L21/0337 , H01L21/32139 , H01L21/76816 , H01L23/498 , H01L29/0692 , H01L45/1691 , H01L2924/0002 , H01L2924/00
摘要： A metal layer is deposited over a material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation or nitridation. A hard mask portion is formed over the metal layer. A plasma impermeable spacer is formed on at least one first sidewall of the hard mask portion, while at least one second sidewall of the hard mask portion is physically exposed. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. A sequence of a surface pull back of the hard mask portion, cavity etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a hole pattern having a spacing that is not limited by lithographic minimum dimensions.
摘要翻译：金属层沉积在材料层上。金属层包括可通过等离子体氧化或氮化转化为含介电金属的化合物的元素金属。在金属层上形成硬掩模部分。在硬掩模部分的至少一个第一侧壁上形成等离子体不可渗透的间隔物，同时硬掩模部分的至少一个第二侧壁物理暴露。进行等离子体氧化或氮化以将金属层的物理暴露表面转化为含介电金属的化合物。重复将硬掩模部分的表面拉回序列，腔蚀刻，另一表面拉回和将顶表面转化为含介电金属的化合物，以形成具有不受光刻最小值限制的间隔的孔图案尺寸。

7. 发明申请

US20140027917A1 NON-LITHOGRAPHIC LINE PATTERN FORMATION 有权
标题翻译：非线性线图形成
公开(公告)号：US20140027917A1
公开(公告)日：2014-01-30
申请号：US13561122
申请日：2012-07-30
申请人： Chiahsun Tseng , David V. Horak , Chun-chen Yeh , Yunpeng Yin
发明人： Chiahsun Tseng , David V. Horak , Chun-chen Yeh , Yunpeng Yin
IPC分类号： H01L21/308 , H01L23/48
CPC分类号： H01L21/3081 , H01L21/02244 , H01L21/02247 , H01L21/02249 , H01L21/02252 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/67063 , Y10T428/24802
摘要： A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions.
摘要翻译：金属层沉积在下层材料层上。金属层包括可通过等离子体氧化和/或氮化转化为含介电金属的化合物的元素金属。在金属层上形成硬掩模部分。进行等离子体氧化或氮化以将金属层的物理暴露表面转化为含介电金属的化合物。重复将硬掩模部分的表面拉回序列，沟槽蚀刻，另一表面拉回和将顶表面转化为含介电金属的化合物，以形成具有不受光刻最小值限制的间隔的线图案尺寸。

8. 发明授权

US08609534B2 Electrical fuse structure and method of fabricating same 有权
标题翻译：电熔丝结构及其制造方法
公开(公告)号：US08609534B2
公开(公告)日：2013-12-17
申请号：US12890941
申请日：2010-09-27
申请人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
IPC分类号： H01L21/4763
CPC分类号： H01L23/5256 , H01L21/76805 , H01L21/76807 , H01L21/76831 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved.
摘要翻译：使用位于金属层顶部的双镶嵌结构来提供高编程效率电熔丝。双镶嵌结构包括图案化电介质材料，其具有位于下面的通孔开口上方并连接到下面的通孔开口的线路开口。通孔开口位于顶部并连接到金属层。双镶嵌结构还包括线路开口和通孔开口内的导电特征。电介质间隔物也存在于线路开口和通孔开口内。介电间隔物存在于图案化电介质材料的垂直侧壁上，并将导电特征与图案化电介质材料分开。在线路开口和通孔开口内的电介质间隔物的存在减少了形成导电特征的区域。因此，提供了节省空间的高编程效率电熔丝。

9. 发明申请

US20130328208A1 DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME 有权
标题翻译：双重对等双向对联方案
公开(公告)号：US20130328208A1
公开(公告)日：2013-12-12
申请号：US13490542
申请日：2012-06-07
申请人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L21/76897 , H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76819 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76883 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.
摘要翻译：在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。之后形成第二电介质材料层。在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。通过对第一和第二介电材料层的介电材料的选择性蚀刻来去除第一电介质盖材料的下部，以形成沿着线沟槽的宽度方向横向限制并沿着宽度方向的第一条金属线。形成双镶嵌线和通孔结构，其包括沿着两个独立的水平方向横向限制的通孔结构。

10. 发明申请

US20130320411A1 BORDERLESS CONTACTS FOR METAL GATES THROUGH SELECTIVE CAP DEPOSITION 审中-公开
公开(公告)号：US20130320411A1
公开(公告)日：2013-12-05
申请号：US13488581
申请日：2012-06-05
申请人： Su-Chen Fan , Balasubramanian S. Haran , David V. Horak , Shom Ponoth , Chih-Chao Yang
发明人： Su-Chen Fan , Balasubramanian S. Haran , David V. Horak , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/78 , H01L21/28247 , H01L21/76834 , H01L21/76897 , H01L29/66545
摘要： A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel portion of the substrate. A metal oxide gate cap is present on an upper surface of the metal gate conductor. The metal oxide composition of the metal oxide gate cap may be zirconium oxide, aluminum oxide, magnesium oxide, hafnium oxide or a combination thereof. Contacts may extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region.

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