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1. 发明授权

US06573137B1 Single sided buried strap 有权
标题翻译：单面埋地带
公开(公告)号：US06573137B1
公开(公告)日：2003-06-03
申请号：US09603442
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jack A. Mandelman , Wolfgang Bergner , Gary B. Bronner , Ulrike Gruening , Stephan Kudelka , Alexander Michaelis , Larry Nesbit , Carl J. Radens , Till Schloesser , Helmut Tews
发明人： Ramachandra Divakaruni , Jack A. Mandelman , Wolfgang Bergner , Gary B. Bronner , Ulrike Gruening , Stephan Kudelka , Alexander Michaelis , Larry Nesbit , Carl J. Radens , Till Schloesser , Helmut Tews
IPC分类号： H01L218242
CPC分类号： H01L27/10864
摘要： A method for clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A barrier material is deposited above a node conductor of the storage capacitor. A layer of silicon is deposited over the barrier material. Dopant ions are implanted at an angle into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.
摘要翻译：一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离环的方法，同时将隔离套环留在深沟槽的其它表面。屏蔽材料沉积在存储电容器的节点导体上方。一层硅沉积在阻挡材料上。掺杂离子以一定角度注入到深沟槽内沉积的硅层中，从而留下沉积的硅沿着深沟槽的一侧被植入。未投影的硅被蚀刻。隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

2. 发明授权

US06440872B1 Method for hybrid DRAM cell utilizing confined strap isolation 失效
标题翻译：混合DRAM单元利用限制带隔离的方法
公开(公告)号：US06440872B1
公开(公告)日：2002-08-27
申请号：US09706468
申请日：2000-11-03
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Stephan Kudelka
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Stephan Kudelka
IPC分类号： H01L2100
CPC分类号： H01L27/10867 , H01L27/10876
摘要： A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects.
摘要翻译：形成混合存储器单元的过程，该混合存储单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。

3. 发明授权

US06437401B1 Structure and method for improved isolation in trench storage cells 失效
标题翻译：用于改善沟槽存储单元隔离的结构和方法
公开(公告)号：US06437401B1
公开(公告)日：2002-08-20
申请号：US09824957
申请日：2001-04-03
申请人： Jack A. Mandelman , Stephan Kudelka , Andreas Knorr , Stephen Rahn , Helmut Tews , Michael Wise
发明人： Jack A. Mandelman , Stephan Kudelka , Andreas Knorr , Stephen Rahn , Helmut Tews , Michael Wise
IPC分类号： H01L2976
CPC分类号： H01L27/1087 , H01L27/10861 , H01L27/10864 , H01L29/945
摘要： A trench capacitor structure for improved charge retention and method of manufacturing thereof are provided. A trench is formed in a p-type conductivity semiconductor substrate. An isolation collar is located in an upper portion of the trench. The substrate adjacent the upper portion of the trench contains a first n+ type conductivity region and a second n+ type conductivity region. These regions each abut a wall of the trench and are separated vertically by a portion of the p-type conductivity semiconductor substrate. A void which encircles the perimeter of the trench is formed into the wall of the trench and is located in the substrate between the first and second n+ type conductivity regions.
摘要翻译：提供了用于改善电荷保留的沟槽电容器结构及其制造方法。在p型导电性半导体衬底中形成沟槽。隔离套环位于沟槽的上部。与沟槽上部相邻的衬底包含第一n +型导电区和第二n +型导电区。这些区域各自邻接沟槽的壁并且被p型导电性半导体衬底的一部分垂直分开。围绕沟槽的周边的空隙形成沟槽的壁，并且位于第一和第二n +型导电区域之间的衬底中。

4. 发明授权

US06605860B1 Semiconductor structures and manufacturing methods 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US06605860B1
公开(公告)日：2003-08-12
申请号：US09597442
申请日：2000-06-20
申请人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Raj Jammy , Ulrike Gruening
发明人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Raj Jammy , Ulrike Gruening
IPC分类号： H01L2906
CPC分类号： H01L21/28202 , H01L21/02164 , H01L21/0217 , H01L21/0223 , H01L21/02238 , H01L21/02247 , H01L21/02255 , H01L21/2822 , H01L21/3144 , H01L21/31658 , H01L27/10864 , H01L29/045 , H01L29/42368 , H01L29/512 , H01L29/513 , H01L29/518 , H01L29/66666 , H01L29/7827 , Y10S257/905
摘要： A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of bon axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the crystallographic plane and another one of such planes being the plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the with substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the plane being oxidized at a higher rate than sidewalls in the plane producing silicon dioxide on the silicon nitride layer having thickness over the plane greater than over the plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.
摘要翻译：一种在硅主体上形成基本上均匀的厚的热生长二氧化硅材料的方法，其独立于凸轮轴。沟槽形成在硅体的表面中，这样的沟槽具有设置在不同结晶平面中的侧壁，这些平面中的一个是100晶体平面，另外一个这样的平面是“10”平面。在侧壁上形成基本均匀的氮化硅层。具有基本上均匀的氮化硅层的沟槽经受硅氧化环境，其中<110>面中的侧壁以比在100平面中的侧壁更高的速率被氧化，在氮化硅层上产生二氧化硅具有比<110>平面上的厚度大于超过<100>平面的厚度。对二氧化硅进行蚀刻以选择性地去除二氧化硅，同时留下基本未蚀刻的氮化硅，从而在<100>平面上除去二氧化硅的一部分，从而暴露氮化硅材料的下面部分，同时留下部分在氮化硅材料的下面部分上的<110>面上的二氧化硅。选择性地去除氮化硅材料的暴露部分以暴露设置在<100>平面中的沟槽的侧壁的下面部分，同时留下设置在设置在<110>平面中的沟槽的侧壁上的氮化硅材料的基本上未蚀刻的部分 >飞机。然后将该结构进行硅氧化环境以在沟槽的侧壁上产生基本均匀的二氧化硅层。

5. 发明授权

US06740555B1 Semiconductor structures and manufacturing methods 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US06740555B1
公开(公告)日：2004-05-25
申请号：US09408248
申请日：1999-09-29
申请人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Raj Jammy , Ulrike Gruening
发明人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Raj Jammy , Ulrike Gruening
IPC分类号： H01L218242
CPC分类号： H01L21/28202 , H01L21/02164 , H01L21/0217 , H01L21/0223 , H01L21/02238 , H01L21/02247 , H01L21/02255 , H01L21/2822 , H01L21/3144 , H01L21/31658 , H01L27/10864 , H01L29/045 , H01L29/42368 , H01L29/512 , H01L29/513 , H01L29/518 , H01L29/66666 , H01L29/7827 , Y10S257/905
摘要： A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the crystallographic plane and another one of such planes being the plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the plane being oxidized at a higher rate than sidewalls in the plane producing silicon dioxide on the silicon nitride layer having thickness over the plane greater than over the plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.
摘要翻译：一种用于在独立于轴的硅体上形成基本上均匀的厚的，热生长的二氧化硅材料的方法。沟槽形成在硅体的表面中，这种沟槽具有设置在不同结晶平面内的侧壁，其中一个这样的平面是<100>结晶平面，另外一个这样的平面是<110>平面。在侧壁上形成基本均匀的氮化硅层。具有基本上均匀的氮化硅层的沟槽经受硅氧化环境，其中<110>面中的侧壁以比在100平面中的侧壁更高的速率被氧化，在氮化硅层上产生二氧化硅，厚度大于<100>平面上的厚度。对二氧化硅进行蚀刻以选择性地去除二氧化硅，同时留下基本未蚀刻的氮化硅，从而在<100>平面上除去二氧化硅的一部分，从而暴露氮化硅材料的下面部分，同时留下部分在氮化硅材料的下面部分上的<110>面上的二氧化硅。选择性地去除氮化硅材料的暴露部分以暴露设置在<100>平面中的沟槽的侧壁的下面部分，同时留下设置在设置在<110>平面中的沟槽的侧壁上的氮化硅材料的基本上未蚀刻的部分 >飞机。然后将该结构进行硅氧化环境以在沟槽的侧壁上产生基本均匀的二氧化硅层。

6. 发明授权

US06486024B1 Integrated circuit trench device with a dielectric collar stack, and method of forming thereof 失效
标题翻译：具有介质套管叠层的集成电路沟槽器件及其形成方法
公开(公告)号：US06486024B1
公开(公告)日：2002-11-26
申请号：US09577102
申请日：2000-05-24
申请人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Ulrike Gruening
发明人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Ulrike Gruening
IPC分类号： H01L218242
CPC分类号： H01L27/10861
摘要： A method of using at least two insulative layers to form the isolation collar of a trench device, and the device formed therefrom. The first layer is preferably an oxide (e.g., silicon dioxide 116) formed on the trench substrate sidewalls, and is formed through a TEOS, LOCOS, or combined TEOS/LOCOS process. Preferably, both the TEOS process and the LOCOS process are used to form the first layer. The second layer is preferably a silicon nitride layer (114) formed on the oxide layer. The multiple layers function as an isolation collar stack for the trench. The dopant penetration barrier properties of the second layer permit the dielectric collar stack to be used as a self aligned mask for subsequent buried plate (120) doping.
摘要翻译：一种使用至少两个绝缘层以形成沟槽器件的隔离套环的方法，以及由其形成的器件。第一层优选是形成在沟槽衬底侧壁上的氧化物（例如，二氧化硅116），并且通过TEOS，LOCOS或组合的TEOS / LOCOS工艺形成。优选地，TEOS工艺和LOCOS工艺都用于形成第一层。第二层优选是形成在氧化物层上的氮化硅层（114）。多层用作沟槽的隔离环叠层。第二层的掺杂剂渗透阻挡性质允许电介质套管叠层用作后续掩埋板（120）掺杂的自对准掩模。

7. 发明授权

US06740595B2 Etch process for recessing polysilicon in trench structures 有权
标题翻译：用于在沟槽结构中凹陷多晶硅的蚀刻工艺
公开(公告)号：US06740595B2
公开(公告)日：2004-05-25
申请号：US10122996
申请日：2002-04-12
申请人： Stephan Kudelka , Helmut Tews , Alexander Michaelis , Uwe Schroeder , Martin Popp , Kristin Schupke , Daniel Koehler
发明人： Stephan Kudelka , Helmut Tews , Alexander Michaelis , Uwe Schroeder , Martin Popp , Kristin Schupke , Daniel Koehler
IPC分类号： H01L21311
CPC分类号： H01L27/1087 , H01L21/30604 , H01L27/10829 , H01L29/66181
摘要： A method for eching a recess in a polysilicon region of a semiconductor device by applying a solution of NH4OH in water to the polysilicon.
摘要翻译：一种通过将NH 4 OH溶液施加到多晶硅中来捕获半导体器件的多晶硅区域中的凹陷的方法。

8. 发明申请

US20050167741A1 ENCAPSULATED SPACERS IN VERTICAL PASS GATE DRAM AND DAMASCENE LOGIC GATES 失效
标题翻译：垂直通道门和大气门逻辑门的封装间隔
公开(公告)号：US20050167741A1
公开(公告)日：2005-08-04
申请号：US10770264
申请日：2004-02-02
申请人： Ramachandra Divakaruni , Stephan Kudelka , Jack Mandelman
发明人： Ramachandra Divakaruni , Stephan Kudelka , Jack Mandelman
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8242 , H01L29/06 , H01L29/423 , H01L29/737 , H01L29/78 , H01L29/76
CPC分类号： H01L29/66537 , H01L21/28114 , H01L27/10864 , H01L27/10876 , H01L27/10891 , H01L29/0692 , H01L29/42376 , H01L29/665 , H01L29/66553 , H01L29/6656 , H01L29/6659 , H01L29/66621 , H01L29/7371 , H01L29/7834
摘要： Semiconductor devices having improved isolation are provided along with methods of fabricating such semiconductor devices. The improved isolation includes an encapsulated spacer formed within a gate region of a device.
摘要翻译：提供具有改进的隔离的半导体器件与制造这种半导体器件的方法一起提供。改进的隔离包括形成在器件的栅极区域内的封装间隔物。

9. 发明授权

US06605838B1 Process flow for thick isolation collar with reduced length 有权
标题翻译：具有减小长度的厚隔离环的工艺流程
公开(公告)号：US06605838B1
公开(公告)日：2003-08-12
申请号：US10261219
申请日：2002-09-30
申请人： Jack A. Mandelman , Rama Divakaruni , Gerd Fehlauer , Stephan Kudelka , Uwe Schroeder , Helmut H. Tews
发明人： Jack A. Mandelman , Rama Divakaruni , Gerd Fehlauer , Stephan Kudelka , Uwe Schroeder , Helmut H. Tews
IPC分类号： H01L27108
CPC分类号： H01L27/10867 , H01L27/10841 , H01L27/10864 , H01L29/66181 , H01L29/945
摘要： A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 &mgr;m or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.
摘要翻译：提供了沟槽电容器存储单元结构，其包括垂直轴环区域，其抑制存在于垂直MOSFET和下面的沟槽电容器之间的相邻垂直寄生晶体管的电流泄漏。具有约0.50μm或更小的垂直长度的垂直环形隔离件包括部分在沟槽外部存在的第一部分和存在于沟槽内部的第二部分。轴环氧化物的第一部分比所述第二部分氧化物厚，从而减少了寄生电流泄漏。

10. 发明申请

US20060172486A1 Selective etching to increase trench surface area 有权
标题翻译：选择性蚀刻以增加沟槽表面积
公开(公告)号：US20060172486A1
公开(公告)日：2006-08-03
申请号：US11047312
申请日：2005-01-31
申请人： Helmut Tews , Stephan Kudelka , Kenneth Settlemyer
发明人： Helmut Tews , Stephan Kudelka , Kenneth Settlemyer
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L21/30604 , H01L29/66181
摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.
摘要翻译：在衬底中形成的沟槽的壁的表面积增加。阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角沟渠墙壁的交叉点。

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