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1. 发明授权

US07915132B2 Corresponding capacitor arrangement and method for making the same 有权
标题翻译：相应的电容器布置及其制造方法
公开(公告)号：US07915132B2
公开(公告)日：2011-03-29
申请号：US12562460
申请日：2009-09-18
申请人： Hans-Joachim Barth , Helmut Tews
发明人： Hans-Joachim Barth , Helmut Tews
IPC分类号： H01L21/20
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a method for producing a capacitor arrangement, and to a corresponding capacitor arrangement, wherein the first insulating layer is formed at the surface of a carrier substrate and a first capacitor electrode with a multiplicity of interspaced first interconnects is produced in said insulating layer. Using a mask layer, partial regions of the first insulating layer are removed for the purpose of uncovering the multiplicity of first interconnects, and after the formation of a capacitor dielectric at the surface of the uncovered first interconnects, a second capacitor electrode is formed with a multiplicity of interspaced second interconnects lying between the first interconnects coated with capacitor dielectric. This additionally simplified production method enables self-aligning and cost-effective production of capacitors having a high capacitance per unit area and mechanical stability.
摘要翻译：本发明涉及一种用于制造电容器装置的方法和相应的电容器装置，其中第一绝缘层形成在载体衬底的表面，并且在所述绝缘体中产生具有多个间隔第一互连的第一电容器电极层。使用掩模层，为了揭露多个第一互连的目的，除去第一绝缘层的部分区域，并且在未覆盖的第一互连件的表面上形成电容器电介质之后，形成第二电容器电极位于涂覆有电容器电介质的第一互连之间的间隔第二互连的多重性。这种另外简化的制造方法能够实现具有每单位面积的高电容和机械稳定性的电容器的自对准和成本有效的生产。

2. 发明申请

US20110012208A1 FIELD-EFFECT TRANSISTOR WITH LOCAL SOURCE/DRAIN INSULATION AND ASSOCIATED METHOD OF PRODUCTION 审中-公开
标题翻译：具有局部源/漏绝缘和相关生产方法的场效应晶体管
公开(公告)号：US20110012208A1
公开(公告)日：2011-01-20
申请号：US12888938
申请日：2010-09-23
申请人： Jüergen Holz , Klaus Schrüfer , Helmut Tews
发明人： Jüergen Holz , Klaus Schrüfer , Helmut Tews
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/283 , H01L21/30604 , H01L21/31 , H01L21/3205 , H01L29/0653 , H01L29/41783
摘要： A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions.
摘要翻译：一种制造具有局部源极/漏极绝缘的场效应晶体管的方法。该方法包括在半导体衬底上形成和图案化具有栅极层和栅极电介质的栅叠层; 在半导体衬底中的栅极堆叠处形成源极和漏极凹陷; 至少在所述源极和漏极凹陷的底部区域中形成凹陷绝缘层; 以及用用于实现源极和漏极区域的填充层填充所述至少部分绝缘的源极和漏极凹部。

3. 发明授权

US07777300B2 Semiconductor device with capacitor 有权
标题翻译：带电容器的半导体器件
公开(公告)号：US07777300B2
公开(公告)日：2010-08-17
申请号：US11856775
申请日：2007-09-18
申请人： Helmut Tews , Hans-Gerd Jetten , Alexander von Glasow , Hans-Joachim Barth
发明人： Helmut Tews , Hans-Gerd Jetten , Alexander von Glasow , Hans-Joachim Barth
IPC分类号： H01L23/52
CPC分类号： H01L23/5223 , H01G4/33 , H01L28/40 , H01L2924/0002 , Y10T29/435 , H01L2924/00
摘要： One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip having a final metal layer; a dielectric layer disposed over the final metal layer; and a conductive layer deposed over the dielectric layer, the dielectric layer being between the final metal layer and the conductive layer.
摘要翻译：一个或多个实施例涉及半导体结构，包括：具有最终金属层的半导体芯片; 设置在最终金属层上的电介质层; 并且导电层设置在电介质层之上，介电层位于最终的金属层和导电层之间。

4. 发明授权

US07767100B2 Patterning method and field effect transistors 有权
标题翻译：图案化方法和场效应晶体管
公开(公告)号：US07767100B2
公开(公告)日：2010-08-03
申请号：US10575916
申请日：2004-09-28
申请人： Rodger Fehlhaber , Helmut Tews
发明人： Rodger Fehlhaber , Helmut Tews
IPC分类号： C25F3/00 , H01L21/336 , H01L21/302 , H01L21/461
CPC分类号： H01L29/7851 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L29/42384 , H01L29/66772 , H01L29/66795
摘要： A patterning method with a filling material with a T-shaped cross section is used as a mask during patterning to produce structures having sublithographic dimensions, such as a double-fin field effect transistor.
摘要翻译：在图案化期间，使用具有T形横截面的填充材料的图案化方法来制造具有亚光刻尺寸的结构，例如双翅片场效应晶体管。

5. 发明授权

US07745875B2 Method for producing a vertical field effect transistor 有权
标题翻译：垂直场效应晶体管的制造方法
公开(公告)号：US07745875B2
公开(公告)日：2010-06-29
申请号：US12143204
申请日：2008-06-20
申请人： Helmut Tews
发明人： Helmut Tews
IPC分类号： H01L29/78
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/28282 , H01L29/66666 , H01L29/66742 , H01L29/66833 , H01L29/7828 , H01L29/78642 , H01L29/7883 , H01L29/7885 , H01L29/792
摘要： A method for producing a field effect transistor, in which a plurality of layers are in each case deposited, planarized and etched back, in particular a gate electrode layer, is disclosed. This method allows the manufacturing of transistors having outstanding electrical properties and having outstanding reproducibility.
摘要翻译：公开了一种场效应晶体管的制造方法，其中在各种情况下沉积，平坦化和回蚀刻多个层，特别是栅极电极层。该方法允许制造具有优异的电性能并具有出色的再现性的晶体管。

6. 发明申请

US20100142266A1 VERTICAL FIELD-EFFECT TRANSISTOR 有权
标题翻译：垂直场效应晶体管
公开(公告)号：US20100142266A1
公开(公告)日：2010-06-10
申请号：US12704287
申请日：2010-02-11
申请人： Ronald Kakoschke , Helmut Tews
发明人： Ronald Kakoschke , Helmut Tews
IPC分类号： G11C16/04 , H01L21/336 , G11C11/34
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L29/66666 , H01L29/7827
摘要： A method produces a vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A “buried” terminal region leads as far as a surface of the semiconductor layer. The field-effect transistor also has a doped terminal region near an opening of the depression as well as the doped terminal region remote from the opening, a control region arranged in the depression, and an electrical insulating region between the control region and the channel region. The terminal region remote from the opening leads as far as a surface containing the opening or is electrically conductively connected to an electrically conductive connection leading to the surface. The control region is arranged in only one depression. The field-effect transistor is a drive transistor at a word line or at a bit line of a memory cell array.
摘要翻译：一种方法产生具有半导体层的垂直场效应晶体管，其中掺杂沟道区沿着凹陷布置。 “埋入”端子区域导通至半导体层的表面。场效应晶体管还具有靠近凹陷的开口的掺杂端子区域以及远离开口的掺杂端子区域，布置在凹陷中的控制区域以及控制区域和沟道区域之间的电绝缘区域。远离开口的端子区域引出至包含开口的表面，或者导电地连接到通向该表面的导电连接。控制区域仅布置在一个凹部中。场效应晶体管是位于存储单元阵列的字线或位线处的驱动晶体管。

7. 发明申请

US20090227083A1 FIELD-EFFECT TRANSISTOR WITH LOCAL SOURCE/DRAIN INSULATION AND ASSOCIATED METHOD OF PRODUCTION 有权
标题翻译：具有局部源/漏绝缘和相关生产方法的场效应晶体管
公开(公告)号：US20090227083A1
公开(公告)日：2009-09-10
申请号：US12431214
申请日：2009-04-28
申请人： Jurgen Holz , Klaus Schrufer , Helmut Tews
发明人： Jurgen Holz , Klaus Schrufer , Helmut Tews
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/283 , H01L21/30604 , H01L21/31 , H01L21/3205 , H01L29/0653 , H01L29/41783
摘要： A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions. Further, the step of forming source and drain depressions at the gate stack in the semiconductor substrate includes that first depressions are formed for realizing channel connection regions in the semiconductor substrate, spacers are formed at the gate stack, and second depressions are formed using the spacers as a mask in the first depressions and in the semiconductor substrate.
摘要翻译：一种制造具有局部源极/漏极绝缘的场效应晶体管的方法。该方法包括在半导体衬底上形成和图案化具有栅极层和栅极电介质的栅叠层; 在半导体衬底中的栅极堆叠处形成源极和漏极凹陷; 至少在所述源极和漏极凹陷的底部区域中形成凹陷绝缘层; 以及用用于实现源极和漏极区域的填充层填充所述至少部分绝缘的源极和漏极凹部。此外，在半导体衬底中的栅极堆叠处形成源极和漏极凹陷的步骤包括形成用于实现半导体衬底中的沟道连接区域的第一凹陷，在栅极堆叠处形成间隔物，并且使用间隔件形成第二凹陷作为第一凹部和半导体衬底中的掩模。

8. 发明申请

US20050280052A1 Field effect transistor with local source/drain insulation and associated method of production 有权
标题翻译：具有局部源极/漏极绝缘的场效应晶体管及相关生产方法
公开(公告)号：US20050280052A1
公开(公告)日：2005-12-22
申请号：US10530634
申请日：2003-09-17
申请人： Jurgen Holz , Klaus Schrufer , Helmut Tews
发明人： Jurgen Holz , Klaus Schrufer , Helmut Tews
IPC分类号： H01L21/336 , H01L29/06 , H01L29/76
CPC分类号： H01L29/66636 , H01L21/283 , H01L21/30604 , H01L21/31 , H01L21/3205 , H01L29/0653 , H01L29/41783
摘要： A field-effect transistor (FET) with local source-drain insulation is described. The FET includes a semiconductor substrate, source and drain depressions, a depression insulation layer, an electrically conductive filling layer, a gate dielectric, and a gate layer. The depression insulation layer is formed at least in bottom regions of the source and drain depressions. The electrically conductive filling layer realizes source and drain regions and fills the source and drain depressions at a surface of the depression insulation layer. The gate dielectric is formed at a substrate surface between the source and drain depressions. The gate layer (is formed at a surface of the gate dielectric. The source and drain depressions have, in an upper region, a widening with a predetermined depth for realizing defined channel connection regions.
摘要翻译：描述了具有局部源极 - 漏极绝缘的场效应晶体管（FET）。 FET包括半导体衬底，源极和漏极凹陷，凹陷绝缘层，导电填充层，栅极电介质和栅极层。凹陷绝缘层至少形成在源极和漏极凹陷的底部区域中。导电填充层实现源极和漏极区域并填充凹陷绝缘层的表面处的源极和漏极凹陷。栅极电介质形成在源极和漏极凹陷之间的衬底表面处。栅极层形成在栅极电介质的表面。源极和漏极凹陷在上部区域中具有用于实现限定的沟道连接区域的预定深度的加宽。

9. 发明申请

US20050106861A1 Resistless lithography method for fabricating fine structures 有权
标题翻译：用于制造精细结构的抗光刻法
公开(公告)号：US20050106861A1
公开(公告)日：2005-05-19
申请号：US10499417
申请日：2002-12-10
申请人： Rodger Fehlhaber , Helmut Tews
发明人： Rodger Fehlhaber , Helmut Tews
IPC分类号： G03F7/20 , B81C1/00 , H01L21/027 , H01L21/033 , H01L21/265 , H01L21/306 , H01L21/308 , H01L21/3213 , H01L21/302 , H01L21/425 , H01L21/461
CPC分类号： B81C1/00396 , G03F1/50 , G03F7/2045 , G03F7/2065 , H01L21/0332 , H01L21/0337 , H01L21/2652 , H01L21/3086 , H01L21/32139
摘要： A resistless lithography method for fabricating fine structures is disclosed. IN an embodiment, a semiconductor mask layer (HM) may be formed on a carrier material (TM, HM′) and a selective ion implantation (I) being effected in order to dope selected regions (1) of the semiconductor mask layer (HM). Wet chemical removal of the non doped regions of the semiconductor mask layer (HM) yields a semiconductor mask which can be used for further patterning. A simple and high precision resistless lithography method for structures smaller than 100 nm is obtained in this way.
摘要翻译：公开了一种用于制造精细结构的抗蚀刻光刻方法。在一个实施例中，可以在载体材料（TM，HM'）和选择性离子注入（I）上形成半导体掩模层（HM），以便掺杂半导体掩模层（HM）的选定区域（1））。半导体掩模层（HM）的非掺杂区域的湿化学去除产生可用于进一步图案化的半导体掩模。以这种方式获得用于小于100nm的结构的简单且高精度的无电阻光刻方法。

10. 发明授权

US6034390A Multi-bit trench capacitor 失效
标题翻译：多位沟槽电容器
公开(公告)号：US6034390A
公开(公告)日：2000-03-07
申请号：US340095
申请日：1999-06-25
申请人： Helmut Tews
发明人： Helmut Tews
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10823 , H01L27/108
摘要： A multi-bit trench capacitor having first and second storage nodes provided in the lower region thereof is described. The storage nodes are separated by a dielectric layer that separates the sensing voltage into upper and lower ranges corresponding to data stored in the first and second storage nodes.
摘要翻译：描述了在其下部区域中设置有第一和第二存储节点的多位沟槽电容器。存储节点由介电层分开，该介电层将感测电压分离成对应于存储在第一和第二存储节点中的数据的上限和下限。

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