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1. 发明授权

US06255900B1 Rapid on chip voltage generation for low power integrated circuits 有权
标题翻译：用于低功率集成电路的快速片上电压产生
公开(公告)号：US06255900B1
公开(公告)日：2001-07-03
申请号：US09284435
申请日：1999-04-12
申请人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , Tien-Shin Ho , I-Long Lee , Tzeng-Hei Shiau , Ray-Lin Wan
发明人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , Tien-Shin Ho , I-Long Lee , Tzeng-Hei Shiau , Ray-Lin Wan
IPC分类号： G05F110
CPC分类号： G11C16/30 , G05F3/242 , G11C5/145 , G11C16/08 , H02M3/07
摘要： An on chip voltage generation circuit is provided suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts). A voltage boost circuit is coupled to the supply voltage input and to a boost signal, which boosts the on-chip voltage at a node on the integrated circuit in response to a transition of the boost signal. The voltage boost circuit has a first mode which in response to the transition boosts the on-chip voltage at a first rate of boosting until a first threshold, and a second mode which in response to the transition boosts the on-chip voltage at a second rate of boosting until a second threshold. The second rate of boosting in the preferred system is slower than the first rate of boosting. A detection circuit is coupled to the node on the integrated circuit which receives the on-chip voltage, and to the voltage boost circuit. The detection circuit signals the voltage boost circuit when the node reaches the first threshold, and signals the voltage boost circuit when the node reaches the second threshold. According to one aspect of the invention, the first threshold is reached within less than 5 nanoseconds, and more preferably about 2 nanoseconds, or less, of the transition in the boost signal.
摘要翻译：提供了适用于具有低电源电压（例如，2.7至3.6伏特）的闪存器件的集成电路的片上电压产生电路。电压升压电路耦合到电源电压输入和升压信号，该升压信号响应于升压信号的转变而升高集成电路上的节点上的片内电压。升压电路具有第一模式，其响应于转换而以第一升压速率提升片上电压直到第一阈值，并且响应于转换的第二模式将片上电压提升到第二阈值升压速率直到第二个阈值。优选系统中的第二次升压速度比第一次升压速率慢。检测电路耦合到接收片上电压的集成电路上的节点和电压升压电路。当节点达到第一阈值时，检测电路向升压电路发信号，当节点达到第二阈值时，信号通知升压电路。根据本发明的一个方面，在升压信号中的转变的小于5纳秒，更优选约2纳秒或更小的范围内达到第一阈值。

2. 发明授权

US06281719B1 Output pad precharge circuit for semiconductor devices 有权
标题翻译：半导体器件的输出焊盘预充电电路
公开(公告)号：US06281719B1
公开(公告)日：2001-08-28
申请号：US09431346
申请日：1999-10-29
申请人： Tien-Shin Ho , Chun-Hsiung Hung , Kuen-Long Chang , I-Long Lee , Ray Lin Wan
发明人： Tien-Shin Ho , Chun-Hsiung Hung , Kuen-Long Chang , I-Long Lee , Ray Lin Wan
IPC分类号： H03B100
CPC分类号： H03K19/01728 , H03K19/00315
摘要： An output driver for an integrated circuit performs a precharge function before internal data is available, minimizing the access time for such data. Also, the pull up and pull down circuitry used in the precharge function is separate from the output driver, and independent of the level of the data signal to be driven. A sense circuit senses an initial state of the output pad, before the output signal is supplied to the output pad, which indicates whether a voltage level on the output pad is above a threshold or below the threshold. A precharge circuit includes a pull up circuit and a pull down circuit. The pull up circuit is responsive to the initial state indicating that the voltage level on the output is below the threshold, and the pull down circuit is responsive to the initial state indicating that the voltage level on the output is above the threshold. A detector is coupled to the output, and produces a control signal indicating when output is near the threshold. Logic is responsive to the control signal from the detector to turn off the precharge circuit when the threshold is reached.
摘要翻译：用于集成电路的输出驱动器在内部数据可用之前执行预充电功能，从而最小化这种数据的访问时间。此外，预充电功能中使用的上拉和下拉电路与输出驱动器分离，并且与要驱动的数据信号的电平无关。在输出信号被提供给输出焊盘之前，感测电路感测输出焊盘的初始状态，其指示输出焊盘上的电压电平是否高于阈值或低于阈值。预充电电路包括上拉电路和下拉电路。上拉电路响应于初始状态，指示输出上的电压电平低于阈值，并且下拉电路响应于初始状态，指示输出上的电压电平高于阈值。检测器耦合到输出端，产生一个控制信号，指示何时输出接近阈值。当达到阈值时，逻辑响应来自检测器的控制信号以关闭预充电电路。

3. 发明授权

US06219290B1 Memory cell sense amplifier 有权
标题翻译：存储单元读出放大器
公开(公告)号：US06219290B1
公开(公告)日：2001-04-17
申请号：US09172274
申请日：1998-10-14
申请人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , I-Long Lee , Yin-Shang Liu , Ray-Lin Wan
发明人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , I-Long Lee , Yin-Shang Liu , Ray-Lin Wan
IPC分类号： G11C702
CPC分类号： G11C7/062 , G11C7/067 , G11C7/12 , G11C16/28
摘要： A sensing circuit for sensing the logic state of a memory cell which minimizes read times is described which includes a first circuit branch corresponding to an array circuit path and a second circuit branch corresponding to a reference cell circuit path. In operation during the pre-decode interval, additional load and current generation circuitry are enabled in the first circuit path so that the voltage as seen by the sensing input of a sensing circuit comparator is driven to be essentially equivalent to that of the reference signal as established by the reference cell circuit path on the reference input of the sensing circuit comparator. Once the address has been decoded, the additional load circuitry is disabled so as to allow the sensing input of the comparator to transition to a voltage representative of the logic state stored in the memory cell.
摘要翻译：描述了用于感测最小化读取时间的存储单元的逻辑状态的感测电路，其包括对应于阵列电路路径的第一电路支路和对应于参考单元电路路径的第二电路支路。在预解码间隔期间的操作中，在第一电路路径中启用额外的负载和电流产生电路，使得感测电路比较器的感测输入所看到的电压被驱动为基本上等于参考信号的电压，如由参考单元电路路径建立在感测电路比较器的参考输入端上。一旦解码了地址，则禁用附加负载电路，以便允许比较器的感测输入转换到代表存储在存储单元中的逻辑状态的电压。

4. 发明授权

US5818764A Block-level wordline enablement to reduce negative wordline stress 失效
标题翻译：块级字词启用以减少负面字线压力
公开(公告)号：US5818764A
公开(公告)日：1998-10-06
申请号：US796821
申请日：1997-02-06
申请人： Tom D. Yiu , I-Long Lee , Kuen-Long Chang , Han-Sung Chen , Tzeng-Huei Shiau , Chun-Hsiung Hung , Ray-Lin Wan
发明人： Tom D. Yiu , I-Long Lee , Kuen-Long Chang , Han-Sung Chen , Tzeng-Huei Shiau , Chun-Hsiung Hung , Ray-Lin Wan
IPC分类号： G11C8/08 , G11C16/08 , G11C16/16 , G11C16/00
CPC分类号： G11C8/08 , G11C16/08 , G11C16/16
摘要： A circuit is provided for supplying a negative erasing voltage onto the wordlines of selected blocks in an array of floating gate memory cells. The circuit includes a voltage circuit, which has a plurality of local outputs, each of which connects to wordlines of an associated block of floating gate memory cells. A block selector circuit is coupled to the local outputs of the voltage circuit and selectively switches each of the local outputs to apply either an erasing voltage or a non-erasing voltage onto the wordlines of the associated block of floating gate memory cells. Negative wordline stress is thus reduced for wordlines of unselected blocks which receive a less negative, non-erasing voltage during block erase operations.
摘要翻译：提供电路，用于向浮动栅极存储单元阵列中的选定块的字线提供负的擦除电压。该电路包括具有多个本地输出的电压电路，每个本地输出连接到浮动栅极存储器单元的相关块的字线。块选择器电路耦合到电压电路的本地输出，并且选择性地切换每个本地输出以将擦除电压或非擦除电压施加到浮动栅极存储器单元的相关联块的字线上。因此，对于在块擦除操作期间接收到较小负的非擦除电压的未选择块的字线，负字线应力减小。

5. 发明授权

US6104665A Enhanced word line driver to reduce gate capacitance for low voltage applications 有权
标题翻译：增强字线驱动器，以降低低电压应用的栅极电容
公开(公告)号：US6104665A
公开(公告)日：2000-08-15
申请号：US269983
申请日：1999-04-05
申请人： Chun Hsiung Hung , I-Long Lee , Tien-Shin Ho , Ray-Lin Wan
发明人： Chun Hsiung Hung , I-Long Lee , Tien-Shin Ho , Ray-Lin Wan
IPC分类号： G11C8/08 , G11C16/08 , G11C8/00
CPC分类号： G11C16/08 , G11C8/08
摘要： An enhanced word line driver circuit suitable for use on integrated circuits such as flash memory devices with voltage boosting includes a load reduction circuit. In response to a boosted voltage, the load reduction circuit decouples a gate capacitance load of deselected enhanced word line drivers from the boost voltage generator. The reduction of capacitive loading decreases power consumption and shortens the voltage boost time of the memory device.
摘要翻译： PCT No.PCT / US98 / 25809 Sec。 371日期1999年4月5日 102（e）1999年4月5日PCT 1998年12月4日提交适用于集成电路的增强型字线驱动电路，例如具有升压的闪存器件，包括负载降低电路。响应于升高的电压，负载降低电路将取消选择的增强型字线驱动器的栅极电容负载与升压电压发生器去耦。电容负载的降低降低了功耗并缩短了存储器件的升压时间。

6. 发明授权

US5745410A Method and system for soft programming algorithm 失效
标题翻译：软编程算法的方法与系统
公开(公告)号：US5745410A
公开(公告)日：1998-04-28
申请号：US619485
申请日：1996-03-21
申请人： Tom Dang-Hsing Yiu , Fuchia Shone , I-Long Lee , Chia-Shing Chen , Hun-Song Chen , Yuan-Chang Liu , Tzeng-Huei Shiau , Kuen-Long Chang , Ray-Lin Wan
发明人： Tom Dang-Hsing Yiu , Fuchia Shone , I-Long Lee , Chia-Shing Chen , Hun-Song Chen , Yuan-Chang Liu , Tzeng-Huei Shiau , Kuen-Long Chang , Ray-Lin Wan
IPC分类号： G11C11/40
CPC分类号： G11C11/40
摘要： A floating gate memory device which includes control circuits to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block. This invention includes repairing the cells by applying a repair pulse to the cell's bit line while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.
摘要翻译： PCT No.PCT / US95 / 15051 Sec。 371日期1996年3月21日 102（e）1996年3月21日PCT 1995年11月17日PCT PCT。第WO97 / 19452号公报日期1997年5月29日一种浮动栅极存储器件，其包括产生修复脉冲以修复过擦除的单元的控制电路，使得它们可以逐块修复。本发明包括通过在维持字线电压高于地面的同时将修复脉冲施加到单元的位线来修复单元。在不同的实施例中，字线电压保持在地面以上两个不同的电压电平。在第一阶段，当施加修复脉冲时，字线电压保持在大约0.1伏和0.2伏之间大约100毫秒。在第二阶段，当施加修复脉冲时，字线电压保持在大约0.4伏和0.5伏之间大约100毫秒。

7. 发明授权

US5963476A Fowler-Nordheim (F-N) tunneling for pre-programming in a floating gate memory device 失效
标题翻译： Fowler-Nordheim（F-N）隧道，用于在浮动栅极存储器件中进行预编程
公开(公告)号：US5963476A
公开(公告)日：1999-10-05
申请号：US975516
申请日：1997-11-12
申请人： Chun Hsiung Hung , Tzeng-Huei Shiau , Yao-Wu Cheng , I-Long Lee , Fuchia Shone , Ray-Lin Wan
发明人： Chun Hsiung Hung , Tzeng-Huei Shiau , Yao-Wu Cheng , I-Long Lee , Fuchia Shone , Ray-Lin Wan
IPC分类号： G11C16/02 , G11C16/04 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/06
CPC分类号： G11C16/107 , G11C16/0416 , G11C16/16 , G11C16/3454 , G11C16/3459 , H01L27/115
摘要： A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows pre-programming by Fowler Nordheim (F-N) tunneling over blocks of cells at a time. The floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included having the first conductivity type. A drain and a source are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain and the source. A floating gate and control gate structure is included over the channel area. The floating gate memory cell is coupled with circuits that induce F-N tunneling of electrons out of the floating gate into the channel area of the substrate for erasing by applying a positive voltage to the second well, such as a voltage higher than the supply voltage, applying a positive voltage to the first well, which is substantially equal to the positive voltage of the second well, applying a negative voltage to the control gate of the cell, while the substrate is grounded. A block wide pre-program operation involves F-N tunneling of electrons into the floating gate from the channel area, using a negative voltage in the second well.
摘要翻译：新的闪存单元结构和操作偏置是基于使用三阱闪存单元，其允许Fowler Nordheim（F-N）一次在单元格块上进行预编程。浮栅存储单元由具有第一导电类型的半导体衬底制成，例如p型。包括具有不同于第一导电类型的第二导电类型的衬底内的第一阱。还包括第一阱中的第二阱具有第一导电类型。在具有第二导电类型的第二阱中形成漏极和源极，并且彼此间隔开以限定漏极和源极之间的沟道区域。通道区域中包括浮动栅极和控制栅极结构。浮动栅极存储单元与电路耦合，该电路通过向第二阱施加正电压，例如高于电源电压的电压，施加电压，使电子从浮动栅极进入隧道区域进入衬底的通道区域以进行擦除与第一阱的正电压相比，其基本上等于第二阱的正电压，而在衬底接地时，向电池的控制栅极施加负电压。块宽的预编程操作涉及使用第二阱中的负电压将电子从沟道区域F-N隧穿到浮置栅极。

8. 发明授权

US6028473A Series capacitor charge pump with dynamic biasing 失效
标题翻译：串联电容充电泵具有动态偏置
公开(公告)号：US6028473A
公开(公告)日：2000-02-22
申请号：US619768
申请日：1996-03-19
申请人： Teruhiko Kamei , Kouta Soejima , I-Long Lee , Ray-Lin Wan
发明人： Teruhiko Kamei , Kouta Soejima , I-Long Lee , Ray-Lin Wan
IPC分类号： H02M3/18
CPC分类号： H02M3/18
摘要： A charge pump apparatus which comprises first and second active capacitors in series, having a common node between them. The second node of the second active capacitor is coupled to a particular node in the charge pump which drives an output of the charge pump. A pump clock is connect to the first lead of the first active capacitor. A voltage clamp is connected to the particular node and provides a bias point. A dynamic biasing circuit is connected to the common node and charges the common node and the particular node during intervals between transitions of the pump clock to keep both the first and second active capacitors activated during the transitions of the pump clock. In a first embodiment, the first and second active capacitors comprise n-channel MOS devices, or equivalents, and the dynamic biasing circuit includes the precharge circuit responsive to a charge clock to pull up the common node during intervals in which the pump clock is low, and wherein the charge clock has transitions which are non-overlapping with transitions of the pump clock. Where the first and second active capacitors comprise p-channel MOS devices, or equivalents, the dynamic biasing circuit includes a precharge circuit responsive to a charge clock to pull down the common node during intervals in which the pump clock is high, and wherein the charge pump has transitions which are non-overlapping with transitions with the pump clock.
摘要翻译： PCT No.PCT / US95 / 03069 Sec。 371日期：1996年3月19日 102（e）1996年3月19日PCT 1995年3月9日PCT PCT。出版物WO96 / 28850 PCT 日期1996年9月19日一种电荷泵装置，其包括串联的第一和第二有源电容器，它们之间具有公共节点。第二有源电容器的第二节点耦合到电荷泵中的特定节点，其驱动电荷泵的输出。泵时钟连接到第一有源电容器的第一引线。电压钳连接到特定节点并提供偏置点。动态偏置电路连接到公共节点，并且在泵时钟的转变之间的间隔期间对公共节点和特定节点进行充电，以在泵时钟的转换期间保持第一和第二有源电容器被激活。在第一实施例中，第一和第二有源电容器包括n沟道MOS器件或等同物，并且动态偏置电路包括响应于充电时钟的预充电电路，以在泵时钟为低的间隔期间上拉公共节点，并且其中所述充电时钟具有与所述泵时钟的转换不重叠的转换。在第一和第二有源电容器包括p沟道MOS器件或等同物的情况下，动态偏置电路包括响应于充电时钟的预充电电路，以在泵时钟为高的间隔期间将公共节点下拉，并且其中充电泵具有与泵时钟的转换不重叠的转换。

9. 发明授权

US07499336B2 Method of programming a nonvolatile memory cell and related memory array 有权
标题翻译：非易失性存储单元和相关存储器阵列的编程方法
公开(公告)号：US07499336B2
公开(公告)日：2009-03-03
申请号：US11748459
申请日：2007-05-14
申请人： Yi-Ching Liu , I-Long Lee , Ming-Hung Chou , Fuja Shone
发明人： Yi-Ching Liu , I-Long Lee , Ming-Hung Chou , Fuja Shone
IPC分类号： G11C16/04
CPC分类号： G11C16/0458 , G11C16/12
摘要： A programming method for programming stored bits in floating gates of a flash memory cell or selected flash memory cells of a flash memory array is utilized for applying SSI injection on said flash memory cell or said selected flash memory cells of a flash memory array is disclosed. Constant charges at the drain regions of said flash memory cell or said selected flash memory cells of the flash memory array is implemented with a capacitor and a related switch for suppressing variant injected-charges-related properties in applying the SSI injection. A constant biasing current, which may be implemented with a constant current source or a current mirror equipped with a constant current source, is applied on source regions of said flash memory cell or said selected flash memory cells of the flash memory array for enhancing the suppression of said variant biasing properties.
摘要翻译：用于对闪速存储器单元的浮动栅极中的存储位进行编程的闪存存储器阵列的选定闪存单元的编程方法被用于在所述闪速存储器单元上施加SSI注入或者闪存阵列的所选闪存单元。闪速存储器阵列的所述闪速存储器单元或所选闪存单元的漏极区域的恒定电荷用电容器和相关开关来实现，用于在应用SSI注入时抑制变型注入电荷相关的特性。可以用恒定电流源或配备有恒定电流源的电流镜来实现的恒定偏置电流被施加在闪速存储器单元的所述闪速存储器单元的所述闪存单元的所述源区域上，或者用于增强抑制的所述变体偏置属性。

10. 发明申请

US20080285342A1 Method of Programming a Nonvolatile Memory Cell and Related Memory Array 有权
标题翻译：非易失性存储器单元和相关存储器阵列的编程方法
公开(公告)号：US20080285342A1
公开(公告)日：2008-11-20
申请号：US11748459
申请日：2007-05-14
申请人： Yi-Ching Liu , I-Long Lee , Ming-Hung Chou , Fuja Shone
发明人： Yi-Ching Liu , I-Long Lee , Ming-Hung Chou , Fuja Shone
IPC分类号： G11C11/34
CPC分类号： G11C16/0458 , G11C16/12
摘要： A programming method for programming stored bits in floating gates of a flash memory cell or selected flash memory cells of a flash memory array is utilized for applying SSI injection on said flash memory cell or said selected flash memory cells of a flash memory array is disclosed. Constant charges at the drain regions of said flash memory cell or said selected flash memory cells of the flash memory array is implemented with a capacitor and a related switch for suppressing variant injected-charges-related properties in applying the SSI injection. A constant biasing current, which may be implemented with a constant current source or a current mirror equipped with a constant current source, is applied on source regions of said flash memory cell or said selected flash memory cells of the flash memory array for enhancing the suppression of said variant biasing properties.
摘要翻译：用于对闪速存储器单元的浮动栅极中的存储位进行编程的闪存存储器阵列的选定闪存单元的编程方法被用于在所述闪速存储器单元上施加SSI注入或者闪存阵列的所选闪存单元。闪速存储器阵列的所述闪速存储器单元或所选闪存单元的漏极区域的恒定电荷用电容器和相关开关来实现，用于在应用SSI注入时抑制变型注入电荷相关的特性。可以用恒定电流源或配备有恒定电流源的电流镜来实现的恒定偏置电流被施加在闪速存储器单元的所述闪速存储器单元的所述闪存单元的所述源区域上，或者用于增强抑制的所述变体偏置属性。

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