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1. 发明授权

US5822243A Dual mode memory with embedded ROM 失效
标题翻译：具有嵌入式ROM的双模存储器
公开(公告)号：US5822243A
公开(公告)日：1998-10-13
申请号：US926342
申请日：1997-09-09
申请人： Fuchia Shone
发明人： Fuchia Shone
IPC分类号： G11C11/00 , G11C11/56 , G11C16/26 , H01L21/8246 , H01L21/8247 , H01L27/115 , G11C14/00
CPC分类号： H01L27/11521 , G11C11/005 , G11C11/5621 , G11C11/5642 , G11C11/5692 , G11C16/26 , H01L27/112 , H01L27/115
摘要： A dual mode memory cell and integrated circuit is provided with a native mode and a ROM mode. ROM code implants are incorporated into a standard memory array. The implants are deep implants which do not have a large effect on the threshold of the cell under normal substrate bias conditions. However, as the substrate bias is increased, they have an increasing effect on the cell threshold. Thus, the cells in one embodiment are floating gate cells that can be read in a flash mode, in which the threshold of the cell is determined predominately by charge stored in the floating gate of the cell, and a read only mode during which a substrate bias is applied, the charge stored in the floating gates in the sector to be read are equalized, and the threshold of the cell is determined predominately by the ROM code implants. Thus, more than one bit per cell is stored in the device, where one bit is stored in a read only mode and another bit is stored in a programmable and erasable mode in each cell in at least one sector of the memory device.
摘要翻译：双模存储单元和集成电路具有本机模式和ROM模式。 ROM代码植入被并入到标准存储器阵列中。植入物是在正常的底物偏置条件下对细胞阈值没有很大影响的深植入物。然而，随着衬底偏压增加，它们对电池阈值的影响越来越大。因此，一个实施例中的单元是浮动栅极单元，其可以以闪存模式读取，其中单元的阈值主要由存储在单元的浮动栅极中的电荷确定，在该模式期间，基板施加偏置，存储在要读取的扇区中的浮动栅极中的电荷相等，并且主要由ROM代码注入来确定单元的阈值。因此，每个单元多于一个位被存储在器件中，其中一个位以只读模式存储，而另一位以存储器件的至少一个扇区中的每个单元中的可编程和可擦除模式存储。

2. 发明授权

US5563823A Fast FLASH EPROM programming and pre-programming circuit design 失效
标题翻译：快速FLASH EPROM编程和预编程电路设计
公开(公告)号：US5563823A
公开(公告)日：1996-10-08
申请号：US393243
申请日：1995-02-23
申请人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
发明人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
IPC分类号： G11C16/10 , G11C16/12 , G11C16/16 , G11C16/24 , G11C7/00
CPC分类号： G11C16/12 , G11C16/10 , G11C16/16 , G11C16/24
摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.
摘要翻译：用于加速浮动存储晶体管（例如FLASH EPROMS）的预编程的电路，并且特别是加速块或阵列的浮置栅极存储晶体管的预编程包括可控电压源，其提供跨控制的栅极编程电位要编程的FLASH EPROM晶体管单元的栅极和源极。提供控制电路，其控制电压源以在编程间隔期间作为时间的函数改变栅极编程电位，以便减少给定量的电荷移动对所选择的浮置栅极晶体管进行编程所需的时间。字线电压是变化的，而源电压保持恒定。通过以较低的字线电压开始，并且在编程间隔期间增加到高字线电压，编程速度增加，并且实现了编程浮栅存储晶体管的高最终导通阈值电压。另外，为了加速预编程，在单个编程间隔期间，编程电位并行应用于四个字线。此外，调整正在编程的单元上的负载以提高编程速度。

3. 发明授权

US5539688A Fast pre-programming circuit for floating gate memory 失效
标题翻译：快速预编程电路用于浮动栅极存储器
公开(公告)号：US5539688A
公开(公告)日：1996-07-23
申请号：US444313
申请日：1995-05-18
申请人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
发明人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
IPC分类号： G11C16/10 , G11C16/12 , G11C16/16 , G11C16/24 , G11C16/06
CPC分类号： G11C16/12 , G11C16/10 , G11C16/16 , G11C16/24
摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.
摘要翻译：用于加速浮动存储晶体管（例如FLASH EPROMS）的预编程的电路，并且特别是加速块或阵列的浮置栅极存储晶体管的预编程包括可控电压源，其提供跨控制的栅极编程电位要编程的FLASH EPROM晶体管单元的栅极和源极。提供控制电路，其控制电压源以在编程间隔期间作为时间的函数改变栅极编程电位，以便减少给定量的电荷移动对所选择的浮置栅极晶体管进行编程所需的时间。字线电压是变化的，而源电压保持恒定。通过以较低的字线电压开始，并且在编程间隔期间增加到高字线电压，编程速度增加，并且实现了编程浮栅存储晶体管的高最终导通阈值电压。另外，为了加速预编程，在单个编程间隔期间，编程电位并行应用于四个字线。此外，调整正在编程的单元上的负载以提高编程速度。

4. 发明授权

US06031771A Memory redundancy circuit using single polysilicon floating gate transistors as redundancy elements 有权
标题翻译：使用单个多晶硅浮栅晶体管作为冗余元件的存储器冗余电路
公开(公告)号：US06031771A
公开(公告)日：2000-02-29
申请号：US158314
申请日：1998-09-21
申请人： Tom D. Yiu , Fuchia Shone
发明人： Tom D. Yiu , Fuchia Shone
IPC分类号： G11C29/00 , H01L27/115 , H01L29/788 , G11C16/06
CPC分类号： G11C29/80 , G11C29/822 , H01L27/115 , H01L29/7885
摘要： A read-only memory device is provided which comprises an array of read-only memory cells arranged in rows and columns. An additional row or column of flat, single polysilicon floating gate memory cells is provided. A row or column decoder coupled to the array of read-only memory cells is responsive to addresses corresponding to rows or columns in the array for selecting addressed rows or columns. Control circuitry including a programmable store for identifying a defective row or column in the array to be replaced by the additional row or column, selects the additional row or column and replaces the defective row or column in response to an address corresponding to the defective row or column. In addition, circuitry is provided on the integrated circuit which allows access to the additional row or column of floating gate memory cells for programming the additional row or column. The additional row or column of floating gate memory cells is comprised of flat or single polysilicon floating gate cells having buried diffusion control gates. This structure is particularly applied to an array of mask ROM cells. Furthermore, the additional row or column of floating gate memory cells can be implemented in layout of mask ROM cells itself, and a very dense compact structure without requiring additional process steps to implement the redundant row or column.
摘要翻译：提供了只读存储器件，其包括以行和列布置的只读存储器单元的阵列。提供了一个额外的行或列的平坦的单个多晶硅浮动栅极存储单元。耦合到只读存储器单元阵列的行或列解码器响应于阵列中对应于行或列的地址，用于选择寻址的行或列。包括可编程存储器的控制电路，用于识别阵列中由附加行或列替换的有缺陷的行或列，选择附加行或列，并响应于与缺陷行相对应的地址替换缺陷行或列，或柱。此外，在集成电路上提供电路，其允许访问用于编程附加行或列的浮动存储单元的附加行或列。浮置栅极存储单元的附加行或列包括具有掩埋扩散控制栅极的平坦或单个多晶硅浮动栅极单元。该结构特别适用于掩模ROM单元阵列。此外，浮动栅极存储器单元的附加行或列可以以掩模ROM单元本身的布局和非常密集的紧凑结构来实现，而不需要额外的处理步骤来实现冗余行或列。

5. 发明授权

US5963476A Fowler-Nordheim (F-N) tunneling for pre-programming in a floating gate memory device 失效
标题翻译： Fowler-Nordheim（F-N）隧道，用于在浮动栅极存储器件中进行预编程
公开(公告)号：US5963476A
公开(公告)日：1999-10-05
申请号：US975516
申请日：1997-11-12
申请人： Chun Hsiung Hung , Tzeng-Huei Shiau , Yao-Wu Cheng , I-Long Lee , Fuchia Shone , Ray-Lin Wan
发明人： Chun Hsiung Hung , Tzeng-Huei Shiau , Yao-Wu Cheng , I-Long Lee , Fuchia Shone , Ray-Lin Wan
IPC分类号： G11C16/02 , G11C16/04 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/06
CPC分类号： G11C16/107 , G11C16/0416 , G11C16/16 , G11C16/3454 , G11C16/3459 , H01L27/115
摘要： A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows pre-programming by Fowler Nordheim (F-N) tunneling over blocks of cells at a time. The floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included having the first conductivity type. A drain and a source are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain and the source. A floating gate and control gate structure is included over the channel area. The floating gate memory cell is coupled with circuits that induce F-N tunneling of electrons out of the floating gate into the channel area of the substrate for erasing by applying a positive voltage to the second well, such as a voltage higher than the supply voltage, applying a positive voltage to the first well, which is substantially equal to the positive voltage of the second well, applying a negative voltage to the control gate of the cell, while the substrate is grounded. A block wide pre-program operation involves F-N tunneling of electrons into the floating gate from the channel area, using a negative voltage in the second well.
摘要翻译：新的闪存单元结构和操作偏置是基于使用三阱闪存单元，其允许Fowler Nordheim（F-N）一次在单元格块上进行预编程。浮栅存储单元由具有第一导电类型的半导体衬底制成，例如p型。包括具有不同于第一导电类型的第二导电类型的衬底内的第一阱。还包括第一阱中的第二阱具有第一导电类型。在具有第二导电类型的第二阱中形成漏极和源极，并且彼此间隔开以限定漏极和源极之间的沟道区域。通道区域中包括浮动栅极和控制栅极结构。浮动栅极存储单元与电路耦合，该电路通过向第二阱施加正电压，例如高于电源电压的电压，施加电压，使电子从浮动栅极进入隧道区域进入衬底的通道区域以进行擦除与第一阱的正电压相比，其基本上等于第二阱的正电压，而在衬底接地时，向电池的控制栅极施加负电压。块宽的预编程操作涉及使用第二阱中的负电压将电子从沟道区域F-N隧穿到浮置栅极。

6. 发明授权

US5699298A Flash memory erase with controlled band-to-band tunneling current 失效
标题翻译：具有受控的带对隧道电流的闪存擦除
公开(公告)号：US5699298A
公开(公告)日：1997-12-16
申请号：US718525
申请日：1996-10-07
申请人： Tzeng-Huei Shiau , Ray-Lin Wan , Yuan-Chang Liu , Chun-Hsiung Hung , Weitong Chuang , Han Sung Chen , Fuchia Shone
发明人： Tzeng-Huei Shiau , Ray-Lin Wan , Yuan-Chang Liu , Chun-Hsiung Hung , Weitong Chuang , Han Sung Chen , Fuchia Shone
IPC分类号： G11C16/16 , G11C16/30 , G11C16/00
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/30
摘要： Substantial reduction in peak current encountered during an erase process for a flash memory device is achieved by selection of source voltage potential during the erase according to the expected band-to-band tunneling current encountered during the process. During the beginning of the process, a lower source voltage potential is selected, which is high enough to cause significant erasing while suppressing band-to-band tunneling current in a portion of the array, and during a second part of the erasing process, a higher source potential is utilized, which ensures successful erasing of the array, without exceeding the peak current requirements of the power supply used with the device. The first and second parts of the erase sequence will induce band-to-band tunneling current in addition to Fowler-Nordheim tunneling current. The band-to-band tunneling current is characterized by a turn on threshold source potential which is inversely related to the threshold of the cell receiving the voltage sequence. The source voltage used in the first part of the erase sequence is set at level that is near or above the turn on threshold source potential for higher threshold cells that are in the high threshold state, but less than the turn on threshold source potential for lower threshold cells in the high threshold state. The source potential in the second part is set at level which is near or above the turn on threshold source potential for lower threshold cells in the high threshold state.
摘要翻译： PCT No.PCT / US96 / 07490 Sec。 371日期1996年10月7日第 102（e）1996年10月7日PCT 1996年5月22日提交闪速存储器件的擦除过程中遇到的峰值电流的实质性降低是通过根据预期的带 - 带来在擦除期间选择源极电压电位来实现的过程中遇到的隧道电流。在该过程开始时，选择较低的源极电压电位，其足够高以引起显着擦除，同时抑制阵列的一部分中的带间隧穿电流，并且在擦除处理的第二部分期间，利用更高的源极电位，确保阵列的成功擦除，而不超过与器件一起使用的电源的峰值电流要求。擦除序列的第一部分和第二部分除了Fowler-Nordheim隧道电流之外还将引起带间隧穿电流。带 - 带隧穿电流的特征在于开启阈值源极电位，其与接收电压序列的电池的阈值成反比。在擦除序列的第一部分中使用的源电压被设置为接近或高于处于高阈值状态的较高阈值电池的阈值源极电位的接通或高于电平，但小于阈值源电位的导通电平较低阈值细胞处于高阈值状态。第二部分中的源极电位被设置在接近或高于阈值电位的阈值源电位的接通或高于在高阈值状态下的较低阈值电池的电位。

7. 发明授权

US5618742A Method of making flash EPROM with conductive sidewall spacer contacting floating gate 失效
标题翻译：制造具有导电侧壁间隔物接触浮动栅极的闪速EPROM的方法
公开(公告)号：US5618742A
公开(公告)日：1997-04-08
申请号：US329487
申请日：1994-10-26
申请人： Fuchia Shone , Tom D.-H. Yiu , Tien-Ler Lin
发明人： Fuchia Shone , Tom D.-H. Yiu , Tien-Ler Lin
IPC分类号： G08G1/017 , G11C16/04 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11519 , G08G1/017 , G11C16/0491 , H01L27/115 , H01L27/11521
摘要： Contactless flash EPROM cell and array designs, and methods for fabricating the same result in dense, segmentable flash EPROM chips. Also, an extended floating gate structure, and method for manufacturing the extended floating gate allow for higher capacitive coupling ratios in flash EPROM circuitry with very small design rules. The floating gates are extended in a symmetrical fashion in a drain-source-drain architecture, so that each pair of columns of cells has a floating gate which is extended in opposite directions from one another. This allows one to take advantage of the space on the cell normally consumed by the isolation regions, to extend the floating gates without increasing the layouts of the cells. Also, an easily scalable design is based on establishing conductive spacers on the sides of floating gate deposition layers which are used for self-alignment of the source and drain. According to this structure, a floating gate deposition is first laid down and used for establishing self-aligned source and drain diffusion regions. After deposition of the source and drain, conductive spacers are deposited on the sides of the first floating gate structure. These conductive spacers can be deposited in a symmetrical fashion, and are easily scalable to large scale arrays of flash EPROM designs.
摘要翻译：非接触式闪存EPROM单元和阵列设计及其制造方法产生致密的，可分割的闪存EPROM芯片。此外，扩展浮动栅极结构和用于制造扩展浮栅的方法允许具有非常小的设计规则的闪存EPROM电路中的较高的电容耦合比。浮置栅极以排列 - 源极 - 漏极结构中的对称方式延伸，使得每对单元电池具有彼此相反方向延伸的浮动栅极。这允许人们利用通常由隔离区域消耗的单元上的空间来扩展浮动栅极而不增加单元的布局。此外，易于扩展的设计是基于在用于源极和漏极的自对准的浮栅沉积层的侧面上建立导电间隔物。根据该结构，首先放置浮置栅极沉积并用于建立自对准的源极和漏极扩散区域。在沉积源极和漏极之后，导电间隔物沉积在第一浮栅结构的侧面上。这些导电间隔物可以以对称的方式沉积，并且易于扩展到闪存EPROM设计的大规模阵列。

8. 发明授权

US6004848A Method of forming a multi-level memory array with channel bias algorithm 失效
标题翻译：使用信道偏置算法形成多级存储器阵列的方法
公开(公告)号：US6004848A
公开(公告)日：1999-12-21
申请号：US927365
申请日：1997-09-09
申请人： Fuchia Shone
发明人： Fuchia Shone
IPC分类号： H01L21/8246 , H01L27/112 , H01L21/8236
CPC分类号： H01L27/1126 , H01L27/112
摘要： A technique for storing multiple bits per cell in a read only memory device, provides for two kinds of code implants in the memory array. A shallow implant such as used in prior art mask ROMs is used for coding a first bit, and a deeper implant is used for coding a second bit in the memory cells. Furthermore, the cells are implemented in a semiconductor substrate so that the channels of the transistors in the mask ROM can be biased. The memory cells include as isolation layer formed in the semiconductor substrate, and a channel well formed in the isolation layer. The device includes resources to apply a first bias potential such as ground, to channel regions of memory cells in the array. When the first bias potential is applied through the channel regions, the memory cells have particular thresholds determined at least in part by the dope concentrations in the channel regions. The device also includes resources to apply a second bias potential to the channel regions of the memory cells. When the second bias potential is applied, a shift in the threshold voltages in the memory cells is induced. The shift in threshold voltage occurs because of the so called body effect, and will be greater in the memory cells which have the deep implants, than in the memory cells which do not have the deep implants. The device also includes wordlines and bitlines by which to read the data stored in the array.
摘要翻译：用于在只读存储器件中存储每个单元的多个位的技术提供了存储器阵列中的两种代码注入。诸如在现有技术的掩模ROM中使用的浅注入被用于对第一位进行编码，而较深的注入用于对存储单元中的第二位进行编码。此外，电池被实现在半导体衬底中，使得掩模ROM中的晶体管的沟道可以被偏置。存储单元包括形成在半导体衬底中的隔离层以及在隔离层中良好地形成的沟道。该装置包括将诸如地的第一偏置电位施加到阵列中的存储器单元的通道区域的资源。当通过沟道区域施加第一偏置电位时，存储器单元具有至少部分地由沟道区域中的掺杂浓度确定的特定阈值。该器件还包括将第二偏置电位施加到存储器单元的沟道区的资源。当施加第二偏置电位时，引起存储单元中阈值电压的偏移。由于所谓的身体效应而产生阈值电压的偏移，并且在具有深度注入的存储器单元中将比在不具有深度注入的存储器单元中更大。该设备还包括读取阵列中存储的数据的字线和位线。

9. 发明授权

US5821909A Fast flash EPROM programming and pre-programming circuit design 失效
公开(公告)号：US5821909A
公开(公告)日：1998-10-13
申请号：US700587
申请日：1996-08-14
申请人： Tom Dang-Hsing Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
发明人： Tom Dang-Hsing Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
IPC分类号： G11C16/10 , G11C16/12 , G11C16/16 , G11C16/24 , G11C16/02
CPC分类号： G11C16/12 , G11C16/10 , G11C16/16 , G11C16/24
摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

10. 发明授权

US5691938A Non-volatile memory cell and array architecture 失效
标题翻译：非易失性存储单元和阵列架构
公开(公告)号：US5691938A
公开(公告)日：1997-11-25
申请号：US237226
申请日：1994-05-03
申请人： Tom Dang-Hsing Yiu , Fuchia Shone , Tien-Ler Lin , Ling Chen
发明人： Tom Dang-Hsing Yiu , Fuchia Shone , Tien-Ler Lin , Ling Chen
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11519 , G11C16/0491 , H01L27/115 , H01L27/11521
摘要： An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is-coupled through a top block select transistor to global bitline. The cell structure uses two metal global bitlines which extend essentially parallel to the drain, source and drain diffusion regions, and a virtual ground conductor which couples a plurality of columns of transistors to a virtual ground terminal through a horizontal conductor, such as a buried diffusion line.
摘要翻译：改进的非接触式EPROM阵列，EPROM单元设计及其制造方法基于唯一的漏极 - 源极 - 漏极配置，其中单个源极扩散由两列晶体管共享。沿着基本上平行的线，在半导体衬底中形成细长的第一漏极扩散区域，细长源极扩散区域和细长的第二漏极扩散区域。场氧化物区域在第一和第二漏极扩散区域的相对侧上生长。浮置栅极和控制栅极字线与漏极 - 源极 - 漏极结构正交形成，以建立具有共享源极区域的两列存储单元。共享源极区域通过底部块选择晶体管耦合到虚拟接地端子。每个漏极扩散区域通过顶部块选择晶体管耦合到全局位线。电池结构使用两个基本平行于漏极，源极和漏极扩散区域延伸的金属全局位线，以及通过水平导体（例如埋入扩散）将多个晶体管列耦合到虚拟接地端子的虚拟接地导体线。

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