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1. 发明授权

US06255900B1 Rapid on chip voltage generation for low power integrated circuits 有权
标题翻译：用于低功率集成电路的快速片上电压产生
公开(公告)号：US06255900B1
公开(公告)日：2001-07-03
申请号：US09284435
申请日：1999-04-12
申请人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , Tien-Shin Ho , I-Long Lee , Tzeng-Hei Shiau , Ray-Lin Wan
发明人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , Tien-Shin Ho , I-Long Lee , Tzeng-Hei Shiau , Ray-Lin Wan
IPC分类号： G05F110
CPC分类号： G11C16/30 , G05F3/242 , G11C5/145 , G11C16/08 , H02M3/07
摘要： An on chip voltage generation circuit is provided suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts). A voltage boost circuit is coupled to the supply voltage input and to a boost signal, which boosts the on-chip voltage at a node on the integrated circuit in response to a transition of the boost signal. The voltage boost circuit has a first mode which in response to the transition boosts the on-chip voltage at a first rate of boosting until a first threshold, and a second mode which in response to the transition boosts the on-chip voltage at a second rate of boosting until a second threshold. The second rate of boosting in the preferred system is slower than the first rate of boosting. A detection circuit is coupled to the node on the integrated circuit which receives the on-chip voltage, and to the voltage boost circuit. The detection circuit signals the voltage boost circuit when the node reaches the first threshold, and signals the voltage boost circuit when the node reaches the second threshold. According to one aspect of the invention, the first threshold is reached within less than 5 nanoseconds, and more preferably about 2 nanoseconds, or less, of the transition in the boost signal.
摘要翻译：提供了适用于具有低电源电压（例如，2.7至3.6伏特）的闪存器件的集成电路的片上电压产生电路。电压升压电路耦合到电源电压输入和升压信号，该升压信号响应于升压信号的转变而升高集成电路上的节点上的片内电压。升压电路具有第一模式，其响应于转换而以第一升压速率提升片上电压直到第一阈值，并且响应于转换的第二模式将片上电压提升到第二阈值升压速率直到第二个阈值。优选系统中的第二次升压速度比第一次升压速率慢。检测电路耦合到接收片上电压的集成电路上的节点和电压升压电路。当节点达到第一阈值时，检测电路向升压电路发信号，当节点达到第二阈值时，信号通知升压电路。根据本发明的一个方面，在升压信号中的转变的小于5纳秒，更优选约2纳秒或更小的范围内达到第一阈值。

2. 发明授权

US06219290B1 Memory cell sense amplifier 有权
标题翻译：存储单元读出放大器
公开(公告)号：US06219290B1
公开(公告)日：2001-04-17
申请号：US09172274
申请日：1998-10-14
申请人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , I-Long Lee , Yin-Shang Liu , Ray-Lin Wan
发明人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , I-Long Lee , Yin-Shang Liu , Ray-Lin Wan
IPC分类号： G11C702
CPC分类号： G11C7/062 , G11C7/067 , G11C7/12 , G11C16/28
摘要： A sensing circuit for sensing the logic state of a memory cell which minimizes read times is described which includes a first circuit branch corresponding to an array circuit path and a second circuit branch corresponding to a reference cell circuit path. In operation during the pre-decode interval, additional load and current generation circuitry are enabled in the first circuit path so that the voltage as seen by the sensing input of a sensing circuit comparator is driven to be essentially equivalent to that of the reference signal as established by the reference cell circuit path on the reference input of the sensing circuit comparator. Once the address has been decoded, the additional load circuitry is disabled so as to allow the sensing input of the comparator to transition to a voltage representative of the logic state stored in the memory cell.
摘要翻译：描述了用于感测最小化读取时间的存储单元的逻辑状态的感测电路，其包括对应于阵列电路路径的第一电路支路和对应于参考单元电路路径的第二电路支路。在预解码间隔期间的操作中，在第一电路路径中启用额外的负载和电流产生电路，使得感测电路比较器的感测输入所看到的电压被驱动为基本上等于参考信号的电压，如由参考单元电路路径建立在感测电路比较器的参考输入端上。一旦解码了地址，则禁用附加负载电路，以便允许比较器的感测输入转换到代表存储在存储单元中的逻辑状态的电压。

3. 发明授权

US5818764A Block-level wordline enablement to reduce negative wordline stress 失效
标题翻译：块级字词启用以减少负面字线压力
公开(公告)号：US5818764A
公开(公告)日：1998-10-06
申请号：US796821
申请日：1997-02-06
申请人： Tom D. Yiu , I-Long Lee , Kuen-Long Chang , Han-Sung Chen , Tzeng-Huei Shiau , Chun-Hsiung Hung , Ray-Lin Wan
发明人： Tom D. Yiu , I-Long Lee , Kuen-Long Chang , Han-Sung Chen , Tzeng-Huei Shiau , Chun-Hsiung Hung , Ray-Lin Wan
IPC分类号： G11C8/08 , G11C16/08 , G11C16/16 , G11C16/00
CPC分类号： G11C8/08 , G11C16/08 , G11C16/16
摘要： A circuit is provided for supplying a negative erasing voltage onto the wordlines of selected blocks in an array of floating gate memory cells. The circuit includes a voltage circuit, which has a plurality of local outputs, each of which connects to wordlines of an associated block of floating gate memory cells. A block selector circuit is coupled to the local outputs of the voltage circuit and selectively switches each of the local outputs to apply either an erasing voltage or a non-erasing voltage onto the wordlines of the associated block of floating gate memory cells. Negative wordline stress is thus reduced for wordlines of unselected blocks which receive a less negative, non-erasing voltage during block erase operations.
摘要翻译：提供电路，用于向浮动栅极存储单元阵列中的选定块的字线提供负的擦除电压。该电路包括具有多个本地输出的电压电路，每个本地输出连接到浮动栅极存储器单元的相关块的字线。块选择器电路耦合到电压电路的本地输出，并且选择性地切换每个本地输出以将擦除电压或非擦除电压施加到浮动栅极存储器单元的相关联块的字线上。因此，对于在块擦除操作期间接收到较小负的非擦除电压的未选择块的字线，负字线应力减小。

4. 发明授权

US6104665A Enhanced word line driver to reduce gate capacitance for low voltage applications 有权
标题翻译：增强字线驱动器，以降低低电压应用的栅极电容
公开(公告)号：US6104665A
公开(公告)日：2000-08-15
申请号：US269983
申请日：1999-04-05
申请人： Chun Hsiung Hung , I-Long Lee , Tien-Shin Ho , Ray-Lin Wan
发明人： Chun Hsiung Hung , I-Long Lee , Tien-Shin Ho , Ray-Lin Wan
IPC分类号： G11C8/08 , G11C16/08 , G11C8/00
CPC分类号： G11C16/08 , G11C8/08
摘要： An enhanced word line driver circuit suitable for use on integrated circuits such as flash memory devices with voltage boosting includes a load reduction circuit. In response to a boosted voltage, the load reduction circuit decouples a gate capacitance load of deselected enhanced word line drivers from the boost voltage generator. The reduction of capacitive loading decreases power consumption and shortens the voltage boost time of the memory device.
摘要翻译： PCT No.PCT / US98 / 25809 Sec。 371日期1999年4月5日 102（e）1999年4月5日PCT 1998年12月4日提交适用于集成电路的增强型字线驱动电路，例如具有升压的闪存器件，包括负载降低电路。响应于升高的电压，负载降低电路将取消选择的增强型字线驱动器的栅极电容负载与升压电压发生器去耦。电容负载的降低降低了功耗并缩短了存储器件的升压时间。

5. 发明授权

US5875152A Address transition detection circuit for a semiconductor memory capable of detecting narrowly spaced address changes 失效
标题翻译：用于能够检测窄间隔地址变化的半导体存储器的地址转换检测电路
公开(公告)号：US5875152A
公开(公告)日：1999-02-23
申请号：US751513
申请日：1996-11-15
申请人： Yin-Shang Liu , Kuen-Long Chang , Chun-Hsiung Hung , Weitong Chuang , Ray-Lin Wan
发明人： Yin-Shang Liu , Kuen-Long Chang , Chun-Hsiung Hung , Weitong Chuang , Ray-Lin Wan
IPC分类号： G11C11/41 , G11C7/22 , G11C8/18 , H03K5/1534 , G11C8/00 , H03K5/22
CPC分类号： H03K5/1534 , G11C7/22 , G11C8/18
摘要： The present invention provides a new (ATD) address transition detection circuit for use on an address bus having any number of address lines. An ATD circuit is disclosed which comprises a first and second circuit and an interval timer. The first circuit has a first and second input and an output. The first circuit receives, at the first input, a change signal corresponding to transitions in one or more addresses of an address bus. In response, the output of the first circuit transitions from an initial first state to a second state. The first circuit is also responsive to a reset command at the second input to return the output to the first state. The interval timer has an output coupled to the second input of the first circuit and an input. The interval timer responsive to an initialize command at the input initiates a timed interval and after the timed interval generates the reset command at the output. The second circuit has an output coupled to the input of the interval timer and an input. The second circuit responsive to the change signal at the input generates an initialize command at the output. The circuit provides a second state at the output of the first circuit, for all including the last received in a series of change signals. This assures that all address transitions have been detected before a memory access is allowed.
摘要翻译：本发明提供一种新的（ATD）地址转换检测电路，用于具有任意数量的地址线的地址总线。公开了一种包括第一和第二电路和间隔定时器的ATD电路。第一电路具有第一和第二输入和输出。第一电路在第一输入端接收对应于地址总线的一个或多个地址中的转变的改变信号。作为响应，第一电路的输出从初始第一状态转变到第二状态。第一电路还响应于第二输入端的复位命令将输出返回到第一状态。间隔定时器具有耦合到第一电路的第二输入和输入的输出。响应于输入的初始化命令的间隔定时器启动定时间隔，并且在定时间隔之后在输出端产生复位命令。第二电路具有耦合到间隔定时器和输入的输入的输出。响应于输入端的变化信号的第二电路在输出端产生初始化命令。该电路在第一电路的输出处提供第二状态，包括在一系列变化信号中最后接收的信号。这确保在允许存储器访问之前已经检测到所有地址转换。

6. 发明授权

US5745410A Method and system for soft programming algorithm 失效
标题翻译：软编程算法的方法与系统
公开(公告)号：US5745410A
公开(公告)日：1998-04-28
申请号：US619485
申请日：1996-03-21
申请人： Tom Dang-Hsing Yiu , Fuchia Shone , I-Long Lee , Chia-Shing Chen , Hun-Song Chen , Yuan-Chang Liu , Tzeng-Huei Shiau , Kuen-Long Chang , Ray-Lin Wan
发明人： Tom Dang-Hsing Yiu , Fuchia Shone , I-Long Lee , Chia-Shing Chen , Hun-Song Chen , Yuan-Chang Liu , Tzeng-Huei Shiau , Kuen-Long Chang , Ray-Lin Wan
IPC分类号： G11C11/40
CPC分类号： G11C11/40
摘要： A floating gate memory device which includes control circuits to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block. This invention includes repairing the cells by applying a repair pulse to the cell's bit line while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.
摘要翻译： PCT No.PCT / US95 / 15051 Sec。 371日期1996年3月21日 102（e）1996年3月21日PCT 1995年11月17日PCT PCT。第WO97 / 19452号公报日期1997年5月29日一种浮动栅极存储器件，其包括产生修复脉冲以修复过擦除的单元的控制电路，使得它们可以逐块修复。本发明包括通过在维持字线电压高于地面的同时将修复脉冲施加到单元的位线来修复单元。在不同的实施例中，字线电压保持在地面以上两个不同的电压电平。在第一阶段，当施加修复脉冲时，字线电压保持在大约0.1伏和0.2伏之间大约100毫秒。在第二阶段，当施加修复脉冲时，字线电压保持在大约0.4伏和0.5伏之间大约100毫秒。

7. 发明授权

US5963476A Fowler-Nordheim (F-N) tunneling for pre-programming in a floating gate memory device 失效
标题翻译： Fowler-Nordheim（F-N）隧道，用于在浮动栅极存储器件中进行预编程
公开(公告)号：US5963476A
公开(公告)日：1999-10-05
申请号：US975516
申请日：1997-11-12
申请人： Chun Hsiung Hung , Tzeng-Huei Shiau , Yao-Wu Cheng , I-Long Lee , Fuchia Shone , Ray-Lin Wan
发明人： Chun Hsiung Hung , Tzeng-Huei Shiau , Yao-Wu Cheng , I-Long Lee , Fuchia Shone , Ray-Lin Wan
IPC分类号： G11C16/02 , G11C16/04 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/06
CPC分类号： G11C16/107 , G11C16/0416 , G11C16/16 , G11C16/3454 , G11C16/3459 , H01L27/115
摘要： A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows pre-programming by Fowler Nordheim (F-N) tunneling over blocks of cells at a time. The floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included having the first conductivity type. A drain and a source are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain and the source. A floating gate and control gate structure is included over the channel area. The floating gate memory cell is coupled with circuits that induce F-N tunneling of electrons out of the floating gate into the channel area of the substrate for erasing by applying a positive voltage to the second well, such as a voltage higher than the supply voltage, applying a positive voltage to the first well, which is substantially equal to the positive voltage of the second well, applying a negative voltage to the control gate of the cell, while the substrate is grounded. A block wide pre-program operation involves F-N tunneling of electrons into the floating gate from the channel area, using a negative voltage in the second well.
摘要翻译：新的闪存单元结构和操作偏置是基于使用三阱闪存单元，其允许Fowler Nordheim（F-N）一次在单元格块上进行预编程。浮栅存储单元由具有第一导电类型的半导体衬底制成，例如p型。包括具有不同于第一导电类型的第二导电类型的衬底内的第一阱。还包括第一阱中的第二阱具有第一导电类型。在具有第二导电类型的第二阱中形成漏极和源极，并且彼此间隔开以限定漏极和源极之间的沟道区域。通道区域中包括浮动栅极和控制栅极结构。浮动栅极存储单元与电路耦合，该电路通过向第二阱施加正电压，例如高于电源电压的电压，施加电压，使电子从浮动栅极进入隧道区域进入衬底的通道区域以进行擦除与第一阱的正电压相比，其基本上等于第二阱的正电压，而在衬底接地时，向电池的控制栅极施加负电压。块宽的预编程操作涉及使用第二阱中的负电压将电子从沟道区域F-N隧穿到浮置栅极。

8. 发明授权

US6087190A Automatic test process with non-volatile result table store 失效
标题翻译：自动测试过程与非易失性结果表存储
公开(公告)号：US6087190A
公开(公告)日：2000-07-11
申请号：US973582
申请日：1997-11-17
申请人： Ray-Lin Wan , Chun-Hsiung Hung , Tzeng-Huei Shiau
发明人： Ray-Lin Wan , Chun-Hsiung Hung , Tzeng-Huei Shiau
IPC分类号： G11C29/24 , G11C29/44 , H10L21/00 , G01R31/26 , H10L21/66
CPC分类号： G11C29/24 , G11C29/44
摘要： A method of manufacturing integrated circuits based on providing a test column of memory cells in the devices. Cells in the test column are selected by a portion of the addresses which identifies a row in the main array on the device. A test is executed to determine a characteristic of the device, and the results of that test are mapped to the portion of the address which identifies a row in the array. This produces a characteristic code address for the device which indicates the results of the test. Access to the test column on the device is enabled, and a bit is written in response to the characteristic code address in a memory cell on the test column. During manufacture the test column is read in order to classify the device according to the characteristic. This allows for storing in a table look-up format, significant amounts of data about the characteristics of the device without requiring large amounts of memory on the device, and substantially relieving the testing system of a requirement for memory resources.
摘要翻译： PCT No.PCT / US97 / 18204 Sec。 371日期：1997年11月17日 102（e）日期1997年11月17日PCT 1997年10月8日PCT公布。公开号WO99 / 18531 日期1999年04月15日基于在器件中提供存储器单元的测试列的制造集成电路的方法。测试列中的单元格由标识设备主阵列中的行的地址的一部分来选择。执行测试以确定设备的特性，并将该测试的结果映射到标识阵列中的一行的地址部分。这产生了指示测试结果的设备的特征代码地址。启用对设备的测试列的访问，并响应于测试列上的存储单元中的特征代码地址写入一个位。在制造期间，读取测试柱以便根据特性对装置进行分类。这允许以表查找格式存储关于设备的特性的大量数据，而不需要设备上的大量存储器，并且基本上减轻了测试系统对存储器资源的需求。

9. 发明授权

US6021069A Bit latch scheme for parallel program verify in floating gate memory device 有权
标题翻译：用于在浮动栅极存储器件中并行程序验证的位锁存方案
公开(公告)号：US6021069A
公开(公告)日：2000-02-01
申请号：US160637
申请日：1998-09-24
申请人： Chun-Hsiung Hung , Ray-Lin Wan
发明人： Chun-Hsiung Hung , Ray-Lin Wan
IPC分类号： G11C16/06
CPC分类号： G11C16/3454
摘要： A method for determining successful programming of a set of memory cells in an array of floating gate memory cells including bit lines coupled with corresponding columns of cells in the array, word lines coupled with corresponding rows of cells in the array, and bit latches coupled to the respective bit lines. The method includes applying a word line voltage to a word line across which memory cells in the set of memory cells are accessible. A potential applied to memory cells in the set of memory cells is raised. A current load is caused from the bit line. Changes in respective voltage levels of bit lines in the set of bit lines are responded to in parallel to store a constant in bit latches in the set of bit latches coupled to bit lines on which the respective voltage levels pass a determinate threshold during the step of applying a word line voltage. An integrated circuit memory is described. The memory includes a device, connected to a bit line and ground, for selectively causing a current flow from the bit line at least before loading a constant into the memory element.
摘要翻译：一种用于确定浮动栅极存储器单元阵列中的一组存储器单元的成功编程的方法，包括与阵列中的相应列的单元阵列耦合的位线，与阵列中的相应的单元行耦合的字线以及耦合到相应的位线。该方法包括将字线电压施加到存储器单元集合中的存储器单元可访问的字线。提高了应用于该组存储器单元中的存储器单元的电位。从位线引起电流负载。位线组中的位线的各个电压电平的变化被并行地响应以存储耦合到位线的位锁存器中的位锁存器中的常数，其中相应的电压电平在其中的各个电压电平通过了确定的阈值应用字线电压。描述集成电路存储器。存储器包括连接到位线和地的器件，用于至少在将常数加载到存储器元件之前选择性地引起来自位线的电流。

10. 发明授权

US06573780B2 Four-phase charge pump with lower peak current 有权
标题翻译：具有较低峰值电流的四相电荷泵
公开(公告)号：US06573780B2
公开(公告)日：2003-06-03
申请号：US09355654
申请日：1999-08-02
申请人： Yu Shen Lin , Chun-Hsiung Hung , Ray-Lin Wan
发明人： Yu Shen Lin , Chun-Hsiung Hung , Ray-Lin Wan
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2003/075
摘要： A four-phase charge pump circuit suitable for use on integrated circuits, such as flash memory devices, includes circuitry that drives charge pump nodes in two components separated by a time delay. The two components can be triggered by edges from the clocks that control the timing of the charge pump. Driving the charge pump nodes in two components separated by a delay decreases the peak current of the charge pump and improves noise characteristics of a voltage supply or ground line connected to the charge pump.
摘要翻译：适用于集成电路（例如闪存器件）的四相电荷泵电路包括驱动由时间延迟分开的两个部件中的电荷泵节点的电路。这两个组件可以由控制电荷泵定时的时钟边沿触发。驱动由延迟分开的两个部件中的电荷泵节点会降低电荷泵的峰值电流，并改善连接到电荷泵的电源或接地线的噪声特性。

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