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1. 发明授权

US07499336B2 Method of programming a nonvolatile memory cell and related memory array 有权
标题翻译：非易失性存储单元和相关存储器阵列的编程方法
公开(公告)号：US07499336B2
公开(公告)日：2009-03-03
申请号：US11748459
申请日：2007-05-14
申请人： Yi-Ching Liu , I-Long Lee , Ming-Hung Chou , Fuja Shone
发明人： Yi-Ching Liu , I-Long Lee , Ming-Hung Chou , Fuja Shone
IPC分类号： G11C16/04
CPC分类号： G11C16/0458 , G11C16/12
摘要： A programming method for programming stored bits in floating gates of a flash memory cell or selected flash memory cells of a flash memory array is utilized for applying SSI injection on said flash memory cell or said selected flash memory cells of a flash memory array is disclosed. Constant charges at the drain regions of said flash memory cell or said selected flash memory cells of the flash memory array is implemented with a capacitor and a related switch for suppressing variant injected-charges-related properties in applying the SSI injection. A constant biasing current, which may be implemented with a constant current source or a current mirror equipped with a constant current source, is applied on source regions of said flash memory cell or said selected flash memory cells of the flash memory array for enhancing the suppression of said variant biasing properties.
摘要翻译：用于对闪速存储器单元的浮动栅极中的存储位进行编程的闪存存储器阵列的选定闪存单元的编程方法被用于在所述闪速存储器单元上施加SSI注入或者闪存阵列的所选闪存单元。闪速存储器阵列的所述闪速存储器单元或所选闪存单元的漏极区域的恒定电荷用电容器和相关开关来实现，用于在应用SSI注入时抑制变型注入电荷相关的特性。可以用恒定电流源或配备有恒定电流源的电流镜来实现的恒定偏置电流被施加在闪速存储器单元的所述闪速存储器单元的所述闪存单元的所述源区域上，或者用于增强抑制的所述变体偏置属性。

2. 发明申请

US20080285342A1 Method of Programming a Nonvolatile Memory Cell and Related Memory Array 有权
标题翻译：非易失性存储器单元和相关存储器阵列的编程方法
公开(公告)号：US20080285342A1
公开(公告)日：2008-11-20
申请号：US11748459
申请日：2007-05-14
申请人： Yi-Ching Liu , I-Long Lee , Ming-Hung Chou , Fuja Shone
发明人： Yi-Ching Liu , I-Long Lee , Ming-Hung Chou , Fuja Shone
IPC分类号： G11C11/34
CPC分类号： G11C16/0458 , G11C16/12
摘要： A programming method for programming stored bits in floating gates of a flash memory cell or selected flash memory cells of a flash memory array is utilized for applying SSI injection on said flash memory cell or said selected flash memory cells of a flash memory array is disclosed. Constant charges at the drain regions of said flash memory cell or said selected flash memory cells of the flash memory array is implemented with a capacitor and a related switch for suppressing variant injected-charges-related properties in applying the SSI injection. A constant biasing current, which may be implemented with a constant current source or a current mirror equipped with a constant current source, is applied on source regions of said flash memory cell or said selected flash memory cells of the flash memory array for enhancing the suppression of said variant biasing properties.
摘要翻译：用于对闪速存储器单元的浮动栅极中的存储位进行编程的闪存存储器阵列的选定闪存单元的编程方法被用于在所述闪速存储器单元上施加SSI注入或者闪存阵列的所选闪存单元。闪速存储器阵列的所述闪速存储器单元或所选闪存单元的漏极区域的恒定电荷用电容器和相关开关来实现，用于在应用SSI注入时抑制变型注入电荷相关的特性。可以用恒定电流源或配备有恒定电流源的电流镜来实现的恒定偏置电流被施加在闪速存储器单元的所述闪速存储器单元的所述闪存单元的所述源区域上，或者用于增强抑制的所述变体偏置属性。

3. 发明申请

US20080181013A1 Method for reading a memory array with a non-volatile memory structure 有权
公开(公告)号：US20080181013A1
公开(公告)日：2008-07-31
申请号：US11669169
申请日：2007-01-31
申请人： Ming-Hung Chou , Fuja Shone
发明人： Ming-Hung Chou , Fuja Shone
IPC分类号： G11C16/06
CPC分类号： G11C16/26 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42328 , H01L29/42332 , H01L29/7887
摘要： A method for reading a memory array is disclosed. The method includes turning on the column of select gates; preprogramming a first right floating gate to a high threshold and a first left floating gate coupled to a same first word line as the first right floating gate to a low threshold; charging a voltage of the right data line to a first predetermined value; charging a voltage of the first word line to a second predetermined value which is between the high threshold of the first right floating gate and the low threshold of the first left floating gate; charging a voltage of a second word line coupled to a second right floating gate to a third predetermined value; and comparing a current of the left data line with a fourth predetermined value.

4. 发明授权

US07450424B2 Method for reading a memory array with a non-volatile memory structure 有权
标题翻译：用非易失性存储器结构读取存储器阵列的方法
公开(公告)号：US07450424B2
公开(公告)日：2008-11-11
申请号：US11669169
申请日：2007-01-31
申请人： Ming-Hung Chou , Fuja Shone
发明人： Ming-Hung Chou , Fuja Shone
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42328 , H01L29/42332 , H01L29/7887
摘要： A method for reading a memory array is disclosed. The method includes turning on the column of select gates; preprogramming a first right floating gate to a high threshold and a first left floating gate coupled to a same first word line as the first right floating gate to a low threshold; charging a voltage of the right data line to a first predetermined value; charging a voltage of the first word line to a second predetermined value which is between the high threshold of the first right floating gate and the low threshold of the first left floating gate; charging a voltage of a second word line coupled to a second right floating gate to a third predetermined value; and comparing a current of the left data line with a fourth predetermined value.
摘要翻译：公开了一种用于读取存储器阵列的方法。该方法包括打开选择门的列; 将第一右浮动栅极预编程为高阈值，将第一左浮动栅极耦合到与第一右浮栅相同的第一字线至低阈值; 将所述右数据线的电压充电到第一预定值; 将第一字线的电压充电到位于第一右浮动栅极的高阈值与第一左浮动栅极的低阈值之间的第二预定值; 将耦合到第二右浮动栅极的第二字线的电压充电至第三预定值; 以及将所述左数据线的电流与第四预定值进行比较。

5. 发明申请

US20130044542A1 METHOD OF SORTING A MULTI-BIT PER CELL NON-VOLATILE MEMORY AND A MULTI-MODE CONFIGURATION METHOD 有权
标题翻译：分配多单元非易失性存储器和多模式配置方法的方法
公开(公告)号：US20130044542A1
公开(公告)日：2013-02-21
申请号：US13210195
申请日：2011-08-15
申请人： Han-Lung Huang , Ming-Hung Chou
发明人： Han-Lung Huang , Ming-Hung Chou
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C16/00 , G11C16/3418 , G11C16/349 , G11C29/44 , G11C29/50004 , G11C2211/5641
摘要： A method of sorting a multi-bit per cell non-volatile memory includes programming and reading to test an n-bit-per-cell (n-bpc) non-volatile memory, which has a plurality of m-bpc pages, where m is a positive integer from 1 through n. If the m-bpc page fails the test, counting a block associated with the failed m-bpc page to (m-1)-bpc blocks, wherein each said m-bpc page is subjected to at most one time of programming and reading. When m is equal to 1, the 0-bpc block corresponds to a bad block.
摘要翻译：一种对每个单元非易失性存储器进行多位排序的方法包括编程和读取以测试具有多个m-bpc页面的n位单元（n-bpc）非易失性存储器，其中m 是从1到n的正整数。如果m-bpc页面未通过测试，则将与失败的m-bpc页面相关联的块计数为（m-1）-bpc块，其中每个所述m-bpc页面经受至多一次编程和读取。当m等于1时，0-bpc块对应于坏块。

6. 发明授权

US08355285B2 Method and system for adaptively finding reference voltages for reading data from a MLC flash memory 有权
标题翻译：用于自适应地寻找用于从MLC闪速存储器读取数据的参考电压的方法和系统
公开(公告)号：US08355285B2
公开(公告)日：2013-01-15
申请号：US12915573
申请日：2010-10-29
申请人： Chien-Fu Huang , Ming-Hung Chou , Han-Lung Huang , Shih-Keng Cho
发明人： Chien-Fu Huang , Ming-Hung Chou , Han-Lung Huang , Shih-Keng Cho
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C2211/5621 , G11C2211/5634
摘要： A method and system for adaptively finding reference voltages for reading data from a multi-level cell (MLC) flash memory is disclosed. According to one embodiment, a first total number of cells of the flash memory above a first threshold voltage in a shifted threshold voltage distribution is provided. Search to find a second threshold voltage such that a second total number of the cells above the second threshold voltage is approximate to the first total number. An initial reference voltage or voltages of the initial threshold voltage distribution are shifted with an amount approximate to a voltage difference between the second threshold voltage and the first threshold voltage, thereby resulting in a new reference voltage or voltages for reading the data from the MLC flash memory.
摘要翻译：公开了一种用于自适应地寻找用于从多电平单元（MLC）闪速存储器读取数据的参考电压的方法和系统。根据一个实施例，提供闪烁存储器中的移位阈值电压分布中高于第一阈值电压的第一总数的单元。搜索以找到第二阈值电压，使得高于第二阈值电压的第二个单元的总数接近于第一总数。初始参考电压或初始阈值电压分布的电压以接近于第二阈值电压和第一阈值电压之间的电压差的量移动，由此导致用于从MLC闪存读取数据的新参考电压或电压记忆。

7. 发明授权

US07848152B1 Method and system for adaptively finding reference voltages for reading data from a MLC flash memory 有权
标题翻译：用于自适应地寻找用于从MLC闪速存储器读取数据的参考电压的方法和系统
公开(公告)号：US07848152B1
公开(公告)日：2010-12-07
申请号：US12464240
申请日：2009-05-12
申请人： Chien-Fu Huang , Ming-Hung Chou , Han-Lung Huang , Shih-Keng Cho
发明人： Chien-Fu Huang , Ming-Hung Chou , Han-Lung Huang , Shih-Keng Cho
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C2211/5621 , G11C2211/5634
摘要： A method and system for adaptively finding reference voltages for reading data from a multi-level cell (MLC) flash memory is disclosed. According to one embodiment, information about an initial threshold voltage distribution is firstly provided. A first threshold voltage in the initial threshold voltage distribution is then associated with a second threshold voltage in a shifted threshold voltage distribution to be determined, such that the information corresponding to the first threshold voltage is approximate to the information corresponding to the second threshold voltage. Accordingly, initial reference voltage or voltages of the initial threshold voltage distribution are shifted with an amount approximate to difference between the first threshold voltage and the second threshold voltage, thereby resulting in new reference voltage or voltages for reading the data from the MLC flash memory.
摘要翻译：公开了一种用于自适应地寻找用于从多电平单元（MLC）闪速存储器读取数据的参考电压的方法和系统。根据一个实施例，首先提供关于初始阈值电压分布的信息。初始阈值电压分布中的第一阈值电压然后与移位的阈值电压分布中的第二阈值电压相关联，以使得与第一阈值电压对应的信息接近于与第二阈值电压对应的信息。因此，初始阈值电压分布的初始参考电压或电压以接近于第一阈值电压和第二阈值电压之间的差值的量移动，由此导致用于从MLC闪速存储器读取数据的新参考电压或电压。

8. 发明授权

US07439133B2 Memory structure and method of manufacturing a memory array 有权
标题翻译：内存结构和制造存储器阵列的方法
公开(公告)号：US07439133B2
公开(公告)日：2008-10-21
申请号：US11306548
申请日：2006-01-02
申请人： Ming-Hung Chou , Fu-Chia Shone
发明人： Ming-Hung Chou , Fu-Chia Shone
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0458 , H01L27/11519 , H01L27/11521
摘要： A memory structure formed between two doping regions in a semiconductor substrate includes two conductive blocks functioning as floating gates formed at two sides of a first conductive line functioning as a select gat and insulated from the first conductive line with two first dielectric spacers therebetween, wherein the two conductive blocks each have a raised top and raised parts of sides relative to the top of the first conductive line. A first dielectric layer is formed on the tops and the parts of the sides of the two conductive blocks. A second conductive line functioning as a word line is formed on the first dielectric layer, wherein the second conductive line has a part deposited between the two conductive blocks and is substantially perpendicular to the first conductive line and two doping region functioning as bit lines.
摘要翻译：在半导体衬底中的两个掺杂区域之间形成的存储器结构包括两个用作浮置栅极的导电块，该栅极形成在用作选择栅的第一导线的两侧，并且与第一导线绝缘，其间具有两个第一介电隔离件，两个导电块各自具有相对于第一导电线的顶部的凸起的顶部和凸起部分的侧面。第一电介质层形成在两个导电块的顶部和侧面的一部分上。用作字线的第二导电线形成在第一电介质层上，其中第二导线具有沉积在两个导电块之间的部分，并且基本上垂直于第一导电线和两个用作位线的掺杂区域。

9. 发明申请

US20080016682A1 Method and apparatus for microstructure assembly 审中-公开
标题翻译：微结构组装方法与装置
公开(公告)号：US20080016682A1
公开(公告)日：2008-01-24
申请号：US11519092
申请日：2006-09-12
申请人： Ming-Hung Chou , Wen-Jey Weng
发明人： Ming-Hung Chou , Wen-Jey Weng
IPC分类号： H05K3/30
CPC分类号： B81C3/002 , B81C2203/058 , H01L21/67005 , H01L24/95 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/12041 , Y10T29/4913 , Y10T29/53174 , H01L2924/00
摘要： A method for microstructure assembly is disclosed, which comprises steps of: providing a carrier having a plurality of joint formed thereon; forming a pedestal on each joint; forming a droplet on each pedestal; placing a microstructure on each droplet; removing each droplet for enabling the corresponding microstructure to couple with the joint corresponding thereto. In the aforesaid method, the use of the plural droplets is to align the plural microstructures in an automatic manner so as to enable each microstructure to couple with its corresponding joint smoothly. In a preferred aspect, an apparatus for microstructure assembly can be provided with respect to the aforesaid method, which is capable of automating the process of microstructure alignment and assembly.
摘要翻译：公开了一种用于微结构组件的方法，其包括以下步骤：提供具有形成在其上的多个接头的载体; 在每个接头上形成基座; 在每个基座上形成液滴; 在每个液滴上放置微结构; 去除每个液滴以使相应的微结构能够与相应的微结构耦合。在上述方法中，多个液滴的使用是以自动方式对准多个微结构，使得每个微结构能够平滑地与其相应的接合部耦合。在一个优选的方面，可以提供一种用于微结构组件的装置，该装置能够使微结构对准和组装的过程自动化。

10. 发明授权

US5912845A Method and circuit for substrate current induced hot e.sup.- injection (SCIHE) approach for V.sub.T convergence at low V.sub.CC voltage 失效
标题翻译：用于在低VCC电压下VT收敛的衬底电流感应热电子注入（SCIHE）方法和电路
公开(公告)号：US5912845A
公开(公告)日：1999-06-15
申请号：US926554
申请日：1997-09-10
申请人： Chia-Shing Chen , Mam-Tsung Wang , Wenpin Lu , Ming-Hung Chou , Ying-Che Lo , Ming-Shang Chen
发明人： Chia-Shing Chen , Mam-Tsung Wang , Wenpin Lu , Ming-Hung Chou , Ying-Che Lo , Ming-Shang Chen
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/107 , G11C16/3404 , G11C16/3409 , G11C16/3445
摘要： A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.
摘要翻译：一种用于软编程存储单元和浮动栅极存储器件的方法。在软编程期间，向控制栅极提供栅极电压，将其提供给漏极的漏极电压，将阱电压提供给阱，并且有源限流器耦合到源极。用于软编程的电路向控制栅极提供栅极电压，将恒定电流源耦合到漏极，将阱电压提供给阱，并将源电压提供给源极。栅极电压可以为约2V，漏极电压可以为约4V，并且阱电压可以为约-2V。根据本发明的另一实施例，栅极电压比漏极电压低约2V，并且阱电压比栅极电压低约4V。

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