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    • 6. 发明授权
    • Plural operation of memory device
    • 存储设备的多种操作
    • US08902656B2
    • 2014-12-02
    • US13750858
    • 2013-01-25
    • Tzung-Shen ChenShuo-Nan HongYi-Ching LiuChun-Hsiung Hung
    • Tzung-Shen ChenShuo-Nan HongYi-Ching LiuChun-Hsiung Hung
    • G11C11/34G11C16/26G11C16/34G11C16/12G11C16/04
    • G11C16/26G11C16/0483G11C16/10G11C16/12G11C16/3422G11C16/3427G11C16/3431
    • An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on the substrate comprising NAND memory cells, and controller circuitry. The first and second memory blocks are configurable to store data for a first pattern of data usage in response to a first operation algorithm to read, program and erase data, and for a second pattern of data usage in response to a second operation algorithm to read, program and erase data, respectively. The controller circuitry is coupled to the first and second memory blocks, and is configured to execute the first and second operation algorithms, wherein a word line pass voltage for read operations applied in the first operation algorithm is at a lower voltage level than a second word line pass voltage for read operations applied in the second operation algorithm.
    • 集成电路器件包括半导体衬底,衬底上的第一存储器块,包括NAND存储器单元,在衬底上的第二存储器块,包括NAND存储器单元,以及控制器电路。 第一和第二存储器块可配置为响应于第一操作算法存储用于第一数据使用模式的数据,以读取,编程和擦除数据,以及响应于第二操作算法读取数据使用的第二模式 ,分别编程和擦除数据。 控制器电路耦合到第一和第二存储器块,并且被配置为执行第一和第二操作算法,其中在第一操作算法中应用的读操作的字线通过电压处于比第二字的较低电压电平 用于在第二操作算法中应用的读操作的线通电压。
    • 9. 发明授权
    • Method of programming a nonvolatile memory cell and related memory array
    • 非易失性存储单元和相关存储器阵列的编程方法
    • US07499336B2
    • 2009-03-03
    • US11748459
    • 2007-05-14
    • Yi-Ching LiuI-Long LeeMing-Hung ChouFuja Shone
    • Yi-Ching LiuI-Long LeeMing-Hung ChouFuja Shone
    • G11C16/04
    • G11C16/0458G11C16/12
    • A programming method for programming stored bits in floating gates of a flash memory cell or selected flash memory cells of a flash memory array is utilized for applying SSI injection on said flash memory cell or said selected flash memory cells of a flash memory array is disclosed. Constant charges at the drain regions of said flash memory cell or said selected flash memory cells of the flash memory array is implemented with a capacitor and a related switch for suppressing variant injected-charges-related properties in applying the SSI injection. A constant biasing current, which may be implemented with a constant current source or a current mirror equipped with a constant current source, is applied on source regions of said flash memory cell or said selected flash memory cells of the flash memory array for enhancing the suppression of said variant biasing properties.
    • 用于对闪速存储器单元的浮动栅极中的存储位进行编程的闪存存储器阵列的选定闪存单元的编程方法被用于在所述闪速存储器单元上施加SSI注入或者闪存阵列的所选闪存单元。 闪速存储器阵列的所述闪速存储器单元或所选闪存单元的漏极区域的恒定电荷用电容器和相关开关来实现,用于在应用SSI注入时抑制变型注入电荷相关的特性。 可以用恒定电流源或配备有恒定电流源的电流镜来实现的恒定偏置电流被施加在闪速存储器单元的所述闪速存储器单元的所述闪存单元的所述源区域上,或者用于增强抑制 的所述变体偏置属性。