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1. 发明授权

US09159434B2 Bit line bias circuit with varying voltage drop 有权
标题翻译：位线偏置电路具有变化的电压降
公开(公告)号：US09159434B2
公开(公告)日：2015-10-13
申请号：US13458485
申请日：2012-04-27
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C16/06 , G11C11/34 , G11C16/26 , G11C7/06 , G11C16/24 , G11C7/12
CPC分类号： G11C16/26 , G11C7/06 , G11C7/065 , G11C7/12 , G11C16/24
摘要： A bit line bias circuit of a memory architecture includes a varying voltage drop. In some embodiments, the voltage drop can depend on the threshold voltage of the memory cell selected to be read, or on the sense current flowing through the memory cell selected to be read.
摘要翻译：存储器架构的位线偏置电路包括变化的电压降。在一些实施例中，电压降可以取决于选择要读取的存储器单元的阈值电压，或取决于流经选择读取的存储器单元的检测电流。

2. 发明授权

US08879332B2 Flash memory with read tracking clock and method thereof 有权
标题翻译：具有读追踪时钟的闪存及其方法
公开(公告)号：US08879332B2
公开(公告)日：2014-11-04
申请号：US13370833
申请日：2012-02-10
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C16/06
摘要： The configurations of a flash memory having a read tracking clock and method thereof are provided. The proposed flash memory includes a first and a second storage capacitors, a first current source providing a first current flowing through the first storage capacitor, a second current source providing a second current flowing through the second storage capacitor, and a comparator electrically connected to the first and the second current sources, and sending out a signal indicating a developing time being accomplished when the second current is larger than the first current.
摘要翻译：提供具有读追踪时钟及其方法的闪速存储器的配置。所提出的闪速存储器包括第一和第二存储电容器，提供流过第一存储电容器的第一电流的第一电流源，提供流过第二存储电容器的第二电流的第二电流源，以及电连接到第一和第二电流源，并且当第二电流大于第一电流时发出指示正在完成的显影时间的信号。

3. 发明授权

US08736358B2 Current source with tunable voltage-current coefficient 有权
标题翻译：具有可调电压 - 电流系数的电流源
公开(公告)号：US08736358B2
公开(公告)日：2014-05-27
申请号：US12840943
申请日：2010-07-21
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/561
摘要： A current source providing an output current with a fixed current range includes a bias circuit, a resistor, a current mirror, and a controller. The bias circuit provides a first voltage weighted with a first tunable coefficient and a second voltage weighted with a second tunable coefficient. The resistor has a tunable resistance for determining a bias current according to a voltage difference between the first and the second voltages and the tunable resistance. The current mirror generates the output current according to the bias current. The controller adjusts the tunable resistance and one of the first and the second tunable coefficients to achieve a voltage-current coefficient with different values, while the bias current and the output current are kept within a fixed current range.
摘要翻译：提供具有固定电流范围的输出电流的电流源包括偏置电路，电阻器，电流镜和控制器。偏置电路提供用第一可调系数和第二可调系数加权的第二电压加权的第一电压。电阻器具有根据第一和第二电压之间的电压差以及可调谐电阻来确定偏置电流的可调电阻。电流镜根据偏置电流产生输出电流。控制器调节可调谐电阻和第一和第二可调谐系数之一，以实现具有不同值的电压 - 电流系数，而偏置电流和输出电流保持在固定电流范围内。

4. 发明授权

US08717813B2 Method and apparatus for leakage suppression in flash memory in response to external commands 有权
标题翻译：响应于外部命令，闪存中泄漏抑制的方法和装置
公开(公告)号：US08717813B2
公开(公告)日：2014-05-06
申请号：US13308266
申请日：2011-11-30
申请人： Nai-Ping Kuo , Su-Chueh Lo , Kuen-Long Chang , Chun-Hsiung Hung , Chia-Feng Cheng , Ken-Hui Chen , Yu-Chen Wang
发明人： Nai-Ping Kuo , Su-Chueh Lo , Kuen-Long Chang , Chun-Hsiung Hung , Chia-Feng Cheng , Ken-Hui Chen , Yu-Chen Wang
IPC分类号： G11C11/34
CPC分类号： G11C16/3409 , G11C11/5635 , G11C16/0483 , G11C16/14
摘要： Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.
摘要翻译：本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。在一个实施例中，闪存器件包括包括多个存储单元块的存储器阵列。该设备还包括用于从存储设备外部的源接收命令的命令接口。该装置还包括控制器，其包括响应于该命令执行泄漏抑制处理的逻辑。泄漏抑制处理包括执行软程序操作以增加给定的存储单元块中的一个或多个过擦除存储器单元的阈值电压并建立擦除状态。

5. 发明授权

US08643404B1 Self-calibration of output buffer driving strength 有权
标题翻译：输出缓冲器自校准驱动强度
公开(公告)号：US08643404B1
公开(公告)日：2014-02-04
申请号：US13556579
申请日：2012-07-24
申请人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen
发明人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen
IPC分类号： H03K3/00
CPC分类号： H03K17/145 , H03K19/00384 , H03K2005/00026
摘要： An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay.
摘要翻译：集成电路包括输出缓冲器和控制电路。输出缓冲器具有信号输入，信号输出和一组控制输入。输出缓冲器具有输出缓冲器延迟，并且响应于施加到该组控制输入的控制信号而可调整驱动强度。控制电路连接到输出缓冲器的一组控制输入。控制电路使用第一和第二定时信号来产生控制信号，并且包括产生具有参考延迟的第一定时信号的参考延迟电路，以及延迟仿真电路，其产生与第二定时信号相关的仿真延迟输出缓冲区延迟。

6. 发明申请

US20130294155A1 PLURAL OPERATION OF MEMORY DEVICE 有权
公开(公告)号：US20130294155A1
公开(公告)日：2013-11-07
申请号：US13750858
申请日：2013-01-25
申请人： Tzung-Shen Chen , Shuo-Nan Hong , Yi-Ching Liu , Chun-Hsiung Hung
发明人： Tzung-Shen Chen , Shuo-Nan Hong , Yi-Ching Liu , Chun-Hsiung Hung
IPC分类号： G11C16/12 , G11C16/26
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3422 , G11C16/3427 , G11C16/3431
摘要： An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on the substrate comprising NAND memory cells, and controller circuitry. The first and second memory blocks are configurable to store data for a first pattern of data usage in response to a first operation algorithm to read, program and erase data, and for a second pattern of data usage in response to a second operation algorithm to read, program and erase data, respectively. The controller circuitry is coupled to the first and second memory blocks, and is configured to execute the first and second operation algorithms, wherein a word line pass voltage for read operations applied in the first operation algorithm is at a lower voltage level than a second word line pass voltage for read operations applied in the second operation algorithm.

7. 发明申请

US20130242665A1 Method and Apparatus for Shortened Erase Operation 有权
标题翻译：用于缩短擦除操作的方法和装置
公开(公告)号：US20130242665A1
公开(公告)日：2013-09-19
申请号：US13536555
申请日：2012-06-28
申请人： Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo , Chin-Hung Chang , Chang-Ting Chen
发明人： Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo , Chin-Hung Chang , Chang-Ting Chen
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/14 , G11C29/34 , G11C2029/2602
摘要： A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.
摘要翻译：非易失性存储器阵列具有不同持续时间的多个擦除过程。可以通过不同的擦除过程之一来擦除阵列的存储器单元的块。

8. 发明授权

US08537630B2 Memory program discharge circuit of bit lines with multiple discharge paths 有权
标题翻译：具有多个放电路径的位线的存储器程序放电电路
公开(公告)号：US08537630B2
公开(公告)日：2013-09-17
申请号：US13722530
申请日：2012-12-20
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/06 , G11C16/24 , G11C16/26 , Y10T29/49117
摘要： A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation.
摘要翻译：存储器集成电路具有非易失性存储单元的阵列，访问非易失性存储单元阵列的位线和位线放电电路。在编程操作期间，位线在同一时间对于位线具有多个放电路径。

9. 发明申请

US20130128670A1 MEMORY ACCESS METHOD AND FLASH MEMORY USING THE SAME 有权
标题翻译：存储器访问方法和使用该存储器的闪存存储器
公开(公告)号：US20130128670A1
公开(公告)日：2013-05-23
申请号：US13298443
申请日：2011-11-17
申请人： Chung-Kuang Chen , Shuo-Nan Hung , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Shuo-Nan Hung , Chun-Hsiung Hung
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/32
摘要： A memory access method is applied in a memory controller for accessing an NAND memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes the following steps. A stream bias signal and a selected word line signal are respectively provided on a selected stream and on a selected cell of the selected stream, and the rest of memory cells are turned on as pass transistors, in the setup phase. A discharge path is provided to eliminate coupling charge presented on unselected streams, in the setup phase. Then, the string select signal is enabled to have the selected stream connected to a sense unit via a metal bit line and according read the selected cell in a voltage sensing scheme, in a read phase, which does not overlap with the setup phase.
摘要翻译：存储器访问方法应用于存储器控制器中，用于访问NAND存储器阵列，包括通过字符串选择信号全局控制的多个相应的选择开关。存储器访问方法包括以下步骤。在所选择的流和所选择的流的所选择的单元上分别提供流偏置信号和选择的字线信号，并且在设置阶段中，剩余的存储器单元作为传输晶体管被导通。提供放电路径以消除在设置阶段中呈现在未选择的流上的耦合电荷。然后，串选择信号被使能以使所选择的流通过金属位线连接到感测单元，并且在读取阶段以读取阶段读取所选择的单元，其不与设置阶段重叠。

10. 发明申请

US20130107637A1 Memory Program Discharge Circuit of Bit Lines With Multiple Discharge Paths 有权
标题翻译：具有多个放电路径的位线的存储器程序放电电路
公开(公告)号：US20130107637A1
公开(公告)日：2013-05-02
申请号：US13722530
申请日：2012-12-20
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C7/12 , G11C7/06
CPC分类号： G11C7/12 , G11C7/06 , G11C16/24 , G11C16/26 , Y10T29/49117
摘要： A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation.
摘要翻译：存储器集成电路具有非易失性存储单元的阵列，访问非易失性存储单元阵列的位线和位线放电电路。在编程操作期间，位线在同一时间对于位线具有多个放电路径。

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