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1. 发明授权

US6031766A Method and circuit for substrate current induced hot e-injection (SCIHE) approach for V.sub.T convergence at low V.sub.cc voltage 有权
标题翻译：用于在低Vcc电压下VT收敛的衬底电流感应热电子注入（SCIHE）方法和电路
公开(公告)号：US6031766A
公开(公告)日：2000-02-29
申请号：US289697
申请日：1999-04-09
申请人： Chia-Shing Chen , Mam-Tsung Wang , Wenpin Lu , Ming-Hung Chou , Ying-Che Lo , Ming-Shang Chen
发明人： Chia-Shing Chen , Mam-Tsung Wang , Wenpin Lu , Ming-Hung Chou , Ying-Che Lo , Ming-Shang Chen
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/107 , G11C16/3404 , G11C16/3409 , G11C16/3445
摘要： A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.
摘要翻译：一种用于软编程存储单元和浮动栅极存储器件的方法。在软编程期间，向控制栅极提供栅极电压，将其提供给漏极的漏极电压，将阱电压提供给阱，并且有源限流器耦合到源极。用于软编程的电路向控制栅极提供栅极电压，将恒定电流源耦合到漏极，将阱电压提供给阱，并将源电压提供给源极。栅极电压可以为约2V，漏极电压可以为约4V，并且阱电压可以为约-2V。根据本发明的另一实施例，栅极电压比漏极电压低约2V，并且阱电压比栅极电压低约4V。

2. 发明授权

US5822242A Asymmetric virtual ground p-channel flash cell with latid n-type pocket and method of fabrication therefor 失效
标题翻译：非对称虚拟地面p沟道闪存单元，带有n型口袋及其制造方法
公开(公告)号：US5822242A
公开(公告)日：1998-10-13
申请号：US812107
申请日：1997-03-05
申请人： Chia-Shing Chen
发明人： Chia-Shing Chen
IPC分类号： G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , G11C13/00
CPC分类号： H01L27/11521 , G11C16/3418 , G11C16/3427 , H01L27/115 , H01L29/7885
摘要： A memory cell having an asymmetric source and drain connection to virtual ground bit-lines providing an abrupt junction suitable for band-to-band hot electron generation and a gradual junction suitable for Fowler-Nordheim tunneling on each side of the cells. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single virtual ground bit line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a semiconductor substrate having a first conductivity type; (3) forming a dielectric covering a semiconductor substrate; (3) forming a first and second column of floating gate cores on the dielectric; (4) implanting a first dopant along a first dopant strip, the first dopant strip aligned between the first and second column and having a second conductivity type opposite the first conductivity type; (5) implanting a second dopant in a second dopant strip aligned with the first diffusion and extending below the second column, the second dopant having an enhancement of the first conductivity type; and (6) completing formation of control gate dielectric and control gates. The presence of asymmetric source and drain diffusions formed thereby improve the isolation between adjacent memory cells and minimizes the disturb problem.
摘要翻译：具有与虚拟接地位线的不对称源极和漏极连接的存储单元，其提供适用于带 - 带热电子产生的突变结，以及适用于细胞每侧的Fowler-Nordheim隧道的逐渐连接。一种非易失性半导体存储器件，包括单元的行和列排列，其中相邻列的单元共享单个虚拟接地位线。一种制造具有不对称源区和漏区的存储单元的方法，包括以下步骤：（1）形成具有第一导电类型的半导体衬底; （3）形成覆盖半导体衬底的电介质; （3）在所述电介质上形成第一和第二列浮栅; （4）沿着第一掺杂剂条移植第一掺杂剂，所述第一掺杂剂条排列在所述第一和第二列之间并且具有与所述第一导电类型相反的第二导电类型; （5）在与所述第一扩散层对准的第二掺杂物条带中注入第二掺杂剂并在所述第二柱的下方延伸，所述第二掺杂物具有所述第一导电类型的增强; （6）完成控制栅介质和控制栅的形成。形成的不对称源极和漏极扩散的存在从而改善了相邻存储器单元之间的隔离并使干扰问题最小化。

3. 发明授权

US5912845A Method and circuit for substrate current induced hot e.sup.- injection (SCIHE) approach for V.sub.T convergence at low V.sub.CC voltage 失效
标题翻译：用于在低VCC电压下VT收敛的衬底电流感应热电子注入（SCIHE）方法和电路
公开(公告)号：US5912845A
公开(公告)日：1999-06-15
申请号：US926554
申请日：1997-09-10
申请人： Chia-Shing Chen , Mam-Tsung Wang , Wenpin Lu , Ming-Hung Chou , Ying-Che Lo , Ming-Shang Chen
发明人： Chia-Shing Chen , Mam-Tsung Wang , Wenpin Lu , Ming-Hung Chou , Ying-Che Lo , Ming-Shang Chen
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/107 , G11C16/3404 , G11C16/3409 , G11C16/3445
摘要： A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.
摘要翻译：一种用于软编程存储单元和浮动栅极存储器件的方法。在软编程期间，向控制栅极提供栅极电压，将其提供给漏极的漏极电压，将阱电压提供给阱，并且有源限流器耦合到源极。用于软编程的电路向控制栅极提供栅极电压，将恒定电流源耦合到漏极，将阱电压提供给阱，并将源电压提供给源极。栅极电压可以为约2V，漏极电压可以为约4V，并且阱电压可以为约-2V。根据本发明的另一实施例，栅极电压比漏极电压低约2V，并且阱电压比栅极电压低约4V。

4. 发明授权

US5751637A Automatic programming algorithm for page mode flash memory with variable programming pulse height and pulse width 失效
标题翻译：用于页面模式闪存的自动编程算法，具有可变编程脉冲高度和脉冲宽度
公开(公告)号：US5751637A
公开(公告)日：1998-05-12
申请号：US605003
申请日：1996-03-12
申请人： Chia Shing Chen , Chun-Hsiung Hung , Ray-Lin Wan , Teruhiko Kamei
发明人： Chia Shing Chen , Chun-Hsiung Hung , Ray-Lin Wan , Teruhiko Kamei
IPC分类号： G11C16/02 , G11C16/10 , G11C13/00
CPC分类号： G11C16/10
摘要： A method for programming a flash memory array which insures fast programming to substantially all of the cells in the array, without over-programming, based on providing a pattern of program retry pulses which have respective pulse widths and pulse heights which vary according to a pattern. The pattern includes a combination of both increasing pulse widths and increasing pulse heights. The pattern includes a first phase which completes in a specified amount of time including a predetermined number of retries so that substantially all of the cells in the array are programmed within the first phase. A second phase of the patter involves a sequence of higher energy pulses addressed to programming the slowest cells in the array. When used in a page program array, in which individual cells which are programmed fast do not receive subsequent retry pulses, a very fast and reliable programming scheme is achieved.
摘要翻译： PCT No.PCT / US95 / 07376 Sec。 371日期：1996年3月12日 102（e）日期1995年6月7日PCT 1996年3月12日提交一种用于对闪速存储器阵列进行编程的方法，其基于提供程序模式确保快速编程到阵列中的基本上所有的阵列中的所有单元，而不需要过度编程具有根据图案变化的相应脉冲宽度和脉冲高度的重试脉冲。该图案包括增加的脉冲宽度和增加的脉冲高度的组合。该模式包括第一阶段，其以指定的时间量完成，包括预定次数的重试，使得阵列中的基本上所有的单元在第一阶段内被编程。图案的第二阶段涉及一系列更高能量的脉冲，寻址到对阵列中最慢的单元进行编程。当在页面程序阵列中使用时，其中被编程为快速的各个单元不接收后续重试脉冲，实现了非常快速和可靠的编程方案。

5. 发明授权

US5745410A Method and system for soft programming algorithm 失效
标题翻译：软编程算法的方法与系统
公开(公告)号：US5745410A
公开(公告)日：1998-04-28
申请号：US619485
申请日：1996-03-21
申请人： Tom Dang-Hsing Yiu , Fuchia Shone , I-Long Lee , Chia-Shing Chen , Hun-Song Chen , Yuan-Chang Liu , Tzeng-Huei Shiau , Kuen-Long Chang , Ray-Lin Wan
发明人： Tom Dang-Hsing Yiu , Fuchia Shone , I-Long Lee , Chia-Shing Chen , Hun-Song Chen , Yuan-Chang Liu , Tzeng-Huei Shiau , Kuen-Long Chang , Ray-Lin Wan
IPC分类号： G11C11/40
CPC分类号： G11C11/40
摘要： A floating gate memory device which includes control circuits to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block. This invention includes repairing the cells by applying a repair pulse to the cell's bit line while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.
摘要翻译： PCT No.PCT / US95 / 15051 Sec。 371日期1996年3月21日 102（e）1996年3月21日PCT 1995年11月17日PCT PCT。第WO97 / 19452号公报日期1997年5月29日一种浮动栅极存储器件，其包括产生修复脉冲以修复过擦除的单元的控制电路，使得它们可以逐块修复。本发明包括通过在维持字线电压高于地面的同时将修复脉冲施加到单元的位线来修复单元。在不同的实施例中，字线电压保持在地面以上两个不同的电压电平。在第一阶段，当施加修复脉冲时，字线电压保持在大约0.1伏和0.2伏之间大约100毫秒。在第二阶段，当施加修复脉冲时，字线电压保持在大约0.4伏和0.5伏之间大约100毫秒。

6. 发明授权

US6130134A Method for forming asymmetric flash EEPROM with a pocket to focus electron injections 有权
标题翻译：用口形成不对称快速EEPROM以聚焦电子注入的方法
公开(公告)号：US6130134A
公开(公告)日：2000-10-10
申请号：US134205
申请日：1998-08-14
申请人： Chia-Shing Chen
发明人： Chia-Shing Chen
IPC分类号： H01L21/265 , H01L21/336 , H01L29/788
CPC分类号： H01L29/66825 , H01L29/7885 , H01L21/26586
摘要： A memory cell having an asymmetric source and drain connection to virtual ground bit-lines. A main diffusion, adjacent the drain and displaced from the source, allows Fowler-Nordheim (FN) tunneling erasure on the drain side of the floating gate. A pocket diffusion, between the main diffusion and the source, concentrates the electric field and thereby enhances the efficiency of programming by electron injection on the source side of the floating gate. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells, in which adjacent columns of cells share a single virtual ground bit line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a semiconductor substrate having a first conductivity type; (2) forming a dielectric covering a semiconductor substrate; (3) forming a first and second column of floating gates on the dielectric; (4) implanting a first dopant along a first dopant strip, the first dopant strip aligned adjacent the first column and displaced from the second column and having a second conductivity type opposite the first conductivity type; (5) implanting a second dopant in a second dopant strip, aligned with the first dopant strip and extending below the second column, the second dopant having an enhancement of the first conductivity type; and (6) completing formation of control gate dielectric and control gates. The manufacturing method of the present invention results in a cell, which increases floating gate memory array density and programming speed while reducing power consumption and the likelihood of a disturb condition.
摘要翻译：具有与虚拟接地位线不对称的源极和漏极连接的存储单元。在漏极附近并从源极偏移的主扩散允许在浮动栅极的漏极侧上的Fowler-Nordheim（FN）隧穿擦除。在主扩散和源之间的口袋扩散集中了电场，从而通过在浮动栅极的源极侧上的电子注入来增强编程的效率。一种非易失性半导体存储器件，包括单元的行和列布置，其中相邻列的单元共享单个虚拟地址位线。一种制造具有不对称源区和漏区的存储单元的方法，包括以下步骤：（1）形成具有第一导电类型的半导体衬底; （2）形成覆盖半导体衬底的电介质; （3）在电介质上形成浮置栅极的第一和第二列; （4）沿着第一掺杂剂条移植第一掺杂剂，所述第一掺杂剂条与所述第一列相邻排列并且从所述第二列移位并具有与所述第一导电类型相反的第二导电类型; （5）在与第一掺杂剂条对准并在第二列下方延伸的第二掺杂剂条中注入第二掺杂剂，第二掺杂剂具有第一导电类型的增强; （6）完成控制栅介质和控制栅的形成。本发明的制造方法产生一个单元，其增加浮动栅极存储器阵列密度和编程速度，同时降低功耗和干扰条件的可能性。

7. 发明授权

US5896314A Asymmetric flash EEPROM with a pocket to focus electron injection and a manufacturing method therefor 失效
标题翻译：具有口袋的不对称闪存EEPROM，用于聚焦电子注入及其制造方法
公开(公告)号：US5896314A
公开(公告)日：1999-04-20
申请号：US812104
申请日：1997-03-05
申请人： Chia-Shing Chen
发明人： Chia-Shing Chen
IPC分类号： H01L21/265 , H01L21/336 , H01L29/788 , G11C13/00
CPC分类号： H01L29/66825 , H01L29/7885 , H01L21/26586
摘要： A memory cell having an asymmetric source and drain connection to virtual ground bit-lines. A main diffusion, adjacent the drain and displaced from the source, allows Fowler-Nordheim (FN) tunneling erasure on the drain side of the floating gate. A pocket diffusion, between the main diffusion and the source, concentrates the electric field and thereby enhances the efficiency of programming by electron injection on the source side of the floating gate. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells, in which adjacent columns of cells share a single virtual ground bit line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a semiconductor substrate having a first conductivity type; (2) forming a dielectric covering a semiconductor substrate; (3) forming a first and second column of floating pates on the dielectric; (4) implanting a first dopant along a first dopant strip, the first dopant strip aligned adjacent the first column and displaced from the second column and having a second conductivity type opposite the first conductivity type; (5) implanting a second dopant in a second dopant strip, aligned with the first dopant strip and extending below the second column, the second dopant having an enhancement of the first conductivity type; and (6) completing formation of control gate dielectric and control gates. The manufacturing method of the present invention results in a cell, which increases floating gate memory array density and programming speed while reducing power consumption and the likelihood of a disturb condition.
摘要翻译：具有与虚拟接地位线不对称的源极和漏极连接的存储单元。在漏极附近并从源极偏移的主扩散允许在浮动栅极的漏极侧上的Fowler-Nordheim（FN）隧穿擦除。在主扩散和源之间的口袋扩散集中了电场，从而通过在浮动栅极的源极侧上的电子注入来增强编程的效率。一种非易失性半导体存储器件，包括单元的行和列布置，其中相邻列的单元共享单个虚拟地址位线。一种制造具有不对称源区和漏区的存储单元的方法，包括以下步骤：（1）形成具有第一导电类型的半导体衬底; （2）形成覆盖半导体衬底的电介质; （3）在所述电介质上形成第一和第二列浮动柱; （4）沿着第一掺杂剂条移植第一掺杂剂，所述第一掺杂剂条与所述第一列相邻排列并且从所述第二列移位并具有与所述第一导电类型相反的第二导电类型; （5）在与第一掺杂剂条对准并在第二列下方延伸的第二掺杂剂条中注入第二掺杂剂，第二掺杂剂具有第一导电类型的增强; （6）完成控制栅介质和控制栅的形成。本发明的制造方法产生一个单元，其增加浮动栅极存储器阵列密度和编程速度，同时降低功耗和干扰条件的可能性。

8. 发明授权

US06211011B1 Method for fabricating asymmetric virtual ground P-channel flash cell 失效
标题翻译：不对称虚拟地面P沟道闪存单元的制造方法
公开(公告)号：US06211011B1
公开(公告)日：2001-04-03
申请号：US09119350
申请日：1998-07-20
申请人： Chia-Shing Chen
发明人： Chia-Shing Chen
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , G11C16/3418 , G11C16/3427 , H01L27/115 , H01L29/7885
摘要： A memory cell having an asymmetric source and drain connection to virtual ground bit-lines providing an abrupt junction suitable for band-to-band hot electron generation and a gradual junction suitable for Fowler-Nordheim tunneling on each side of the cells. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single virtual ground bit line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a semiconductor substrate having a first conductivity type; (3) forming a dielectric covering a semiconductor substrate; (3) forming a first and second column of floating gate cores on the dielectric; (4) implanting a first dopant along a first dopant strip, the first dopant strip aligned between the first and second column and having a second conductivity type opposite the first conductivity type; (5) implanting a second dopant in a second dopant strip aligned with the first diffusion and extending below the second column, the second dopant having an enhancement of the first conductivity type; and (6) completing formation of control gate dielectric and control gates. The presence of asymmetric source and drain diffusions formed thereby improve the isolation between adjacent memory cells and minimizes the disturb problem.
摘要翻译：具有与虚拟接地位线的不对称源极和漏极连接的存储单元，其提供适用于带 - 带热电子产生的突变结，以及适用于细胞每侧的Fowler-Nordheim隧道的逐渐连接。一种非易失性半导体存储器件，包括单元的行和列排列，其中相邻列的单元共享单个虚拟接地位线。一种制造具有不对称源区和漏区的存储单元的方法，包括以下步骤：（1）形成具有第一导电类型的半导体衬底; （3）形成覆盖半导体衬底的电介质; （3）在所述电介质上形成第一和第二列浮栅; （4）沿着第一掺杂剂条移植第一掺杂剂，所述第一掺杂剂条排列在所述第一和第二列之间并且具有与所述第一导电类型相反的第二导电类型; （5）在与所述第一扩散层对准的第二掺杂物条带中注入第二掺杂剂并在所述第二柱的下方延伸，所述第二掺杂物具有所述第一导电类型的增强; （6）完成控制栅介质和控制栅的形成。形成的不对称源极和漏极扩散的存在从而改善了相邻存储器单元之间的隔离并使干扰问题最小化。

9. 发明授权

US5912844A Method for flash EEPROM data writing 失效
标题翻译：闪存EEPROM数据写入方法
公开(公告)号：US5912844A
公开(公告)日：1999-06-15
申请号：US015606
申请日：1998-01-28
申请人： Chia-Shing Chen , Mam-Tsung Wang
发明人： Chia-Shing Chen , Mam-Tsung Wang
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/3459 , G11C16/10
摘要： Method for writing data to a NOR-type flash memory array including loading page data to a bit-latch buffer, programming cells to low threshold voltage V.sub.t, and programming cells to high V.sub.t. Programming cells to high V.sub.t by either: Channel Hot Electron Injection (CHEI) or Source Side Injection (SSI). CHEI releases the band-to-band induced hot hole damage while SSI further reduces the sector size to be the same as page size for NOR-type flash EEPROM memory.
摘要翻译：将数据写入NOR型闪存阵列的方法，包括将页面数据加载到位锁存缓冲器，将单元编程为低阈值电压Vt，并将单元编程为高Vt。通过以下方式将单元编程为高Vt：通道热电子注入（CHEI）或源侧注射（SSI）。 CHEI释放频带到频带引起的热孔损坏，而SSI进一步将扇区大小与NOR型闪存EEPROM存储器的页面大小相同。

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