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1. 发明授权

US06754126B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US06754126B2
公开(公告)日：2004-06-22
申请号：US10106597
申请日：2002-03-27
申请人： Shusaku Yamaguchi , Toshiya Uchida , Yoshimasa Yagishita , Yoshihide Bando , Masahiro Yada , Masaki Okuda , Hiroyuki Kobayashi , Kota Hara , Shinya Fujioka , Waichiro Fujieda
发明人： Shusaku Yamaguchi , Toshiya Uchida , Yoshimasa Yagishita , Yoshihide Bando , Masahiro Yada , Masaki Okuda , Hiroyuki Kobayashi , Kota Hara , Shinya Fujioka , Waichiro Fujieda
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C8/12 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4087 , G11C2211/4061 , G11C2211/4062
摘要： A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.
摘要翻译：形成多个第一存储块和用于再现第一存储块的数据的第二存储块。当读命令和刷新命令彼此冲突时，读控制电路根据刷新命令访问第一存储块，并通过使用第二存储块再现读数据。当写命令和刷新命令彼此冲突时，写控制电路根据命令接收的顺序操作存储块。因此，可以在不被用户识别的情况下进行刷新操作。即，可以提供用户友好的半导体存储器。

2. 发明授权

US06728157B2 Semiconductor memory 有权
公开(公告)号：US06728157B2
公开(公告)日：2004-04-27
申请号：US10335948
申请日：2003-01-03
申请人： Yoshimasa Yagishita , Toshiya Uchida , Yoshihide Bando , Hiroyuki Kobayashi , Shusaku Yamaguchi , Masaki Okuda
发明人： Yoshimasa Yagishita , Toshiya Uchida , Yoshihide Bando , Hiroyuki Kobayashi , Shusaku Yamaguchi , Masaki Okuda
IPC分类号： G11C700
CPC分类号： G11C11/4087 , G11C11/406
摘要： A plurality of memory blocks is allocated the same address spaces to write the same data therein, and is operable independently of one another. One of the memory blocks is selected as a refresh block that performs a refresh operation, in response to a refresh command, while another one of the memory blocks is selected as a read block that performs a read operation, in response to a read command. Then, the plurality of memory blocks performs read operations at different timings so that the read operations overlap one another. Therefore, the semiconductor memory can receive read commands at intervals each of which is shorter than the execution time of a single read operation. As a result, externally supplied read commands can be responded to at high speed, and the data transmission rate during read operation can be improved.

3. 发明授权

US06427197B1 Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations 有权
标题翻译：半导体存储器件与时钟信号同步工作，用于高速数据写入和数据读取操作
公开(公告)号：US06427197B1
公开(公告)日：2002-07-30
申请号：US09394891
申请日：1999-09-13
申请人： Yasuharu Sato , Tadao Aikawa , Shinya Fujioka , Waichiro Fujieda , Hitoshi Ikeda , Hiroyuki Kobayashi
发明人： Yasuharu Sato , Tadao Aikawa , Shinya Fujioka , Waichiro Fujieda , Hitoshi Ikeda , Hiroyuki Kobayashi
IPC分类号： G11C800
CPC分类号： G11C7/1072 , G11C7/1039
摘要： The present invention is a memory circuit for writing prescribed numbers of bits of write data, determined according to the burst length, in response to write command, comprising: a first stage for inputting, and then holding, row addresses and column addresses simultaneously with the write command; a second stage having a memory core connected to the first stage via a pipeline switch, wherein the row addresses and column addresses are decoded, and word line and sense amps are activated; a third stage for inputting the write data serially and sending the write data to the memory core in parallel; and a serial data detection circuit for generating write-pipeline control signal for making the pipeline switch conduct, after the prescribed number of bits of write data has been inputted. According to the present invention, in an FCRAM exhibiting a pipeline structure, the memory core in the second stage can be activated after safely fetching the write data in the burst length. When writing successively or reading successively, moreover, the command cycle can made short irrespective of the burst length.
摘要翻译：本发明是一种存储电路，用于响应于写命令，写入根据突发长度确定的指定数量的写入数据，包括：第一级，用于与第一级同时输入，然后保持行地址和列地址写命令第二级具有经由流水线开关连接到第一级的存储器核，其中行地址和列地址被解码，字线和检测放大器被激活; 用于串行输入写入数据并且将写入数据并行地发送到存储器核心的第三级; 以及串行数据检测电路，用于在输入了规定数量的写入数据之后，产生用于使流水线开关导通的写入流水线控制信号。根据本发明，在呈现流水线结构的FCRAM中，可以在以突发长度安全地取出写入数据之后激活第二级中的存储器核心。此外，当连续写入或连续读取时，无论突发长度如何，命令循环可以变短。

4. 发明授权

US08588006B2 Semiconductor memory including switching circuit for selecting data supply 有权
标题翻译：半导体存储器包括用于选择数据提供的切换电路
公开(公告)号：US08588006B2
公开(公告)日：2013-11-19
申请号：US13570158
申请日：2012-08-08
申请人： Hiroyuki Kobayashi , Toshiya Uchida
发明人： Hiroyuki Kobayashi , Toshiya Uchida
IPC分类号： G11C7/10
CPC分类号： G11C11/4096 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C11/4076 , G11C2207/105
摘要： A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal.
摘要翻译：提供半导体存储器，其包括：第一焊盘; 邻近所述第一焊盘设置的第二焊盘; 耦合到所述第一焊盘的第一输出缓冲器; 以及耦合到第二焊盘的第二输出缓冲器。第一垫通过金属耦合到第二垫。

5. 发明申请

US20060092752A1 Multiple chip package and IC chips 有权
标题翻译：多芯片封装和IC芯片
公开(公告)号：US20060092752A1
公开(公告)日：2006-05-04
申请号：US11043993
申请日：2005-01-28
申请人： Fusao Seki , Tatsushi Otsuka , Masanori Kurita , Shinnosuke Kamata , Toshiya Uchida , Hiroyoshi Tomita , Hiroyuki Kobayashi
发明人： Fusao Seki , Tatsushi Otsuka , Masanori Kurita , Shinnosuke Kamata , Toshiya Uchida , Hiroyoshi Tomita , Hiroyuki Kobayashi
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C5/063 , H01L2224/49113 , H01L2924/3011 , H01L2924/00
摘要： A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a memory chip at portion near the side and the other side respectively. The clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad. A plurality of clock signals are supplied from the logic chip to the memory chip, and a plurality of return clock signals are returned from the memory chip to the logic chip.
摘要翻译：时钟输出板和返回时钟接收焊盘设置在集成电路芯片的靠近侧面的部分和与集成电路芯片的与侧面相反的另一侧的部分的逻辑芯片上。时钟接收垫分别在靠近侧面和另一侧的部分设置在存储器芯片上。时钟接收板电连接到时钟输出板和返回时钟接收板。多个时钟信号从逻辑芯片提供给存储器芯片，并且多个返回时钟信号从存储器芯片返回到逻辑芯片。

6. 发明授权

US08264881B2 Semiconductor memory including pads coupled to each other 有权
标题翻译：半导体存储器包括彼此耦合的焊盘
公开(公告)号：US08264881B2
公开(公告)日：2012-09-11
申请号：US12624764
申请日：2009-11-24
申请人： Hiroyuki Kobayashi , Toshiya Uchida
发明人： Hiroyuki Kobayashi , Toshiya Uchida
IPC分类号： G11C7/00
CPC分类号： G11C11/4096 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C11/4076 , G11C2207/105
摘要： A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal.
摘要翻译：提供半导体存储器，其包括：第一焊盘; 邻近所述第一焊盘设置的第二焊盘; 耦合到所述第一焊盘的第一输出缓冲器; 以及耦合到第二焊盘的第二输出缓冲器。第一垫通过金属耦合到第二垫。

7. 发明授权

US08077537B2 Memory device, memory controller and memory system 有权
标题翻译：内存设备，内存控制器和内存系统
公开(公告)号：US08077537B2
公开(公告)日：2011-12-13
申请号：US12612215
申请日：2009-11-04
申请人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1027 , G11C8/12 , G11C11/40618 , G11C11/4087
摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.
摘要翻译：提供了一种存储装置，其中已经解决了由存储装置的刷新操作引起的有效带宽的减少，存储装置的存储器控制器及其存储器系统。响应于来自存储器控制器的命令操作的存储器件具有分别具有存储器核心的多个存储体，包括存储器单元阵列和解码器，并且由存储体地址选择; 以及控制电路，其响应于后台刷新命令使由所述存储器控制器设置的刷新对象组内的存储器核心依次执行对应于由所述存储器控制器设置的刷新突发长度的次数的刷新操作，并且响应于正常操作命令，在由存储器核心执行的刷新操作期间进一步使存储器内的存储器核心在刷新对象组之外并由存储体地址选择以执行与正常操作命令相对应的正常存储器操作在刷新目标银行。

8. 发明授权

US08004921B2 Memory device, memory controller and memory system 有权
公开(公告)号：US08004921B2
公开(公告)日：2011-08-23
申请号：US12612247
申请日：2009-11-04
申请人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1027 , G11C8/12 , G11C11/40618 , G11C11/4087
摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

9. 发明申请

US20100172200A1 MEMORY DEVICE, MEMORY CONTROLLER AND MEMORY SYSTEM 有权
标题翻译：存储器件，存储器控制器和存储器系统
公开(公告)号：US20100172200A1
公开(公告)日：2010-07-08
申请号：US12612247
申请日：2009-11-04
申请人： Tomohiro KAWAKUBO , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Tomohiro KAWAKUBO , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/406 , G11C7/1027 , G11C8/12 , G11C11/40618 , G11C11/4087
摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.
摘要翻译：提供了一种存储装置，其中已经解决了由存储装置的刷新操作引起的有效带宽的减少，存储装置的存储器控制器及其存储器系统。响应于来自存储器控制器的命令操作的存储器件具有分别具有存储器核心的多个存储体，包括存储器单元阵列和解码器，并且由存储体地址选择; 以及控制电路，其响应于后台刷新命令使由所述存储器控制器设置的刷新对象组内的存储器核心依次执行对应于由所述存储器控制器设置的刷新突发长度的次数的刷新操作，并且响应于正常操作命令，在由存储器核心执行的刷新操作期间进一步使存储器内的存储器核心在刷新对象组之外并由存储体地址选择以执行与正常操作命令相对应的正常存储器操作在刷新目标银行。

10. 发明授权

US07668040B2 Memory device, memory controller and memory system 有权
标题翻译：内存设备，内存控制器和内存系统
公开(公告)号：US07668040B2
公开(公告)日：2010-02-23
申请号：US11707252
申请日：2007-02-16
申请人： Hitoshi Ikeda , Takahiko Sato , Tatsuya Kanda , Toshiya Uchida , Hiroyuki Kobayashi , Satoru Shirakawa , Tetsuo Miyamoto , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Hitoshi Ikeda , Takahiko Sato , Tatsuya Kanda , Toshiya Uchida , Hiroyuki Kobayashi , Satoru Shirakawa , Tetsuo Miyamoto , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C7/10
CPC分类号： G11C8/12 , G06F12/0207
摘要： The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.
摘要翻译：存储器件具有：多个存储体，每个存储体具有存储单元阵列，该存储单元阵列具有分别由行地址选择的多个页面区域，并且每个区域由银行地址选择; 行控制器，其响应于第一操作码来控制每个存储体内的页面区域的激活; 和一组数据输入/输出端子。基于列地址访问每个激活的页面区域内的存储单元区域。行控制器响应于与第一命令一起提供的多存储体信息数据和提供的库地址，为多个存储体生成存储体激活信号，并且响应于第一指令生成多个存储体的行地址提供的银行地址和提供的行地址。响应于行激活信号和由行地址计算器生成的行地址，多个存储体激活页面区域。

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