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    • 6. 发明授权
    • Clock-synchronized memory device and the scheduler thereof
    • 时钟同步存储器件及其调度器
    • US6067632A
    • 2000-05-23
    • US116249
    • 1998-07-16
    • Shusaku Yamaguchi
    • Shusaku Yamaguchi
    • G11C11/407G11C7/10G11C19/00G06F1/04G06F12/00
    • G11C7/1072
    • The present invention provides inside a scheduler a shift register, which performs a shift operation in synch with an external clock, or a clock generated thereby. Then, for example, when controlling latency from the supply of a command until the start of a column operation, at the time the command is supplied, a column access signal is stored in a shift register location, which corresponds to its latency. Because the shift register performs a shift operation in synch with a clock, a column access signal is outputted subsequent to a number of clock pulses, which correspond to its latency. A column control circuit, in response to the timing at which this column access signal is outputted, acquires a column address and other data required for a column circuitry operation, and starts a column circuitry operation. A configuration such as this simplifies the operation of the scheduler. In the above-described shift register, setting an internal operation command signal, which starts a prescribed internal operation, makes it possible to readily manage latency up until the start of an arbitrary internal operation.
    • 本发明在调度器内提供移位寄存器,该移位寄存器执行与外部时钟同步的移位操作或由此产生的时钟。 然后,例如,当控制从提供命令直到列操作开始的等待时间时,在提供命令时,将列存取信号存储在对应于其等待时间的移位寄存器位置。 因为移位寄存器执行与时钟同步的移位操作,所以在与其等待时间对应的多个时钟脉冲之后输出列访问信号。 列控制电路响应于输出该列访问信号的定时,获取列电路操作所需的列地址和其他数据,并开始列电路操作。 这样的配置简化了调度器的操作。 在上述移位寄存器中,设定开始规定的内部动作的内部动作指令信号使得可以容易地管理等待时间直至开始任意的内部操作。
    • 8. 发明授权
    • Semiconductor integrated circuit system
    • 半导体集成电路系统
    • US5874853A
    • 1999-02-23
    • US863356
    • 1997-05-27
    • Shusaku YamaguchiAtsushi HatakeyamaMasato TakitaTadao AikawaHirohiko Mochizuki
    • Shusaku YamaguchiAtsushi HatakeyamaMasato TakitaTadao AikawaHirohiko Mochizuki
    • G11C11/413G11C11/407G11C11/409H03K17/22H03L7/00
    • H03K17/223Y10T307/724
    • A semiconductor integrated circuit system includes a first power line which supplies a first source power voltage, and a second power line which supplies a second source power voltage. A first edge detecting unit outputs a first edge detection signal when a rising edge of the first source power voltage is detected. A second edge detecting unit outputs a second edge detection signal when a rising edge of the second source power voltage is detected. An output unit is connected to the first power line, and outputs data to a data terminal in a data output cycle and sets the data terminal in a high-impedance state in response to the first edge detection signal. An output control unit is connected to the second power line, and controls the output unit in accordance with a read-data signal in the data output cycle, and controls the output unit in response to the second edge detection signal, so that the data terminal is set in the high-impedance state by the output unit.
    • 半导体集成电路系统包括提供第一源电源电压的第一电源线和提供第二源电源电压的第二电源线。 当检测到第一源电源电压的上升沿时,第一边缘检测单元输出第一边沿检测信号。 当检测到第二源电源电压的上升沿时,第二边缘检测单元输出第二边缘检测信号。 输出单元连接到第一电力线,并且在数据输出周期中向数据终端输出数据,并且响应于第一边缘检测信号将数据端子设置为高阻抗状态。 输出控制单元连接到第二电力线,并且根据数据输出周期中的读取数据信号来控制输出单元,并且响应于第二边缘检测信号来控制输出单元,使得数据终端 通过输出单元设置在高阻抗状态。