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    • 1. 发明申请
    • SEMICONDUCTOR MEMORY, SYSTEM, AND METHOD OF OPERATING SEMICONDUCTOR MEMORY
    • 半导体存储器,系统和操作半导体存储器的方法
    • US20120327734A1
    • 2012-12-27
    • US13485266
    • 2012-05-31
    • Takahiko SATO
    • Takahiko SATO
    • G11C5/14
    • G11C11/4074G11C5/14G11C11/40615G11C11/4072
    • A memory has memory cells in a matrix; a first selection unit selecting any of first signal lines in the memory cells, in response to an access request; a second selection unit selecting any of second signal lines in the memory cells, after the first selection unit starts operating; a first voltage generation unit generating a first power supply voltage supplied to the first selection unit; a second voltage generation unit generating a second power supply voltage supplied to the second selection unit, when a start-up signal is active; a switch short-circuiting first and second power supply lines, when a short-circuit signal is active; and a power supply voltage control unit which activates the start-up signal in response to the access request, activates the short-circuit signal after a predetermined time elapses since activation of the start-up signal, deactivates the short-circuit signal and the start-up signal after completion of access operations.
    • 存储器具有矩阵中的存储器单元; 第一选择单元,响应于访问请求,选择存储单元中的第一信号线中的任一个; 在第一选择单元开始操作之后,第二选择单元选择存储单元中的第二信号线中的任一个; 产生提供给第一选择单元的第一电源电压的第一电压产生单元; 第二电压产生单元,当启动信号有效时,产生提供给第二选择单元的第二电源电压; 当短路信号有效时,开关短路第一和第二电源线; 以及电源电压控制单元,其响应于所述访问请求而激活所述启动信号,在启动所述启动信号之后经过预定时间后激活所述短路信号,停用所述短路信号和所述启动 完成访问操作后的up信号。
    • 4. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF ALLOCATING CODES
    • 半导体集成电路和分配代码的方法
    • US20080304333A1
    • 2008-12-11
    • US12136453
    • 2008-06-10
    • Takahiko SATO
    • Takahiko SATO
    • G11C7/00
    • G11C29/02G11C29/021G11C29/028
    • A semiconductor integrated circuit includes a plurality of terminals, a first latch configured to, upon being uniquely specified by a first predetermined number of bits that are part of a plurality of bits entered through the terminals, store a second predetermined number of bits that are at least part of remaining bits left after excluding the first predetermined number of bits from the plurality of bits, and a second latch configured to, upon being uniquely specified by a third predetermined number of bits that are part of the plurality of bits entered through the terminals, store a fourth predetermined number of bits that are at least part of remaining bits left after excluding the third predetermined number of bits from the plurality of bits, wherein the first predetermined number is different from the third predetermined number, and the second predetermined number is different from the fourth predetermined number.
    • 半导体集成电路包括多个终端,第一锁存器被配置为在由作为通过终端输入的多个比特的一部分的第一预定数量的比特唯一地指定时,存储第二预定数量的比特, 在从多个比特排除第一预定数量的比特之后剩下的剩余比特的剩余比特中的至少一部分,以及第二锁存器,被配置为在由作为通过终端输入的多个比特的一部分的第三预定数量的比特唯一地指定 存储从所述多个比特中排除所述第三预定比特数之后的剩余比特的剩余比特的至少一部分的第四预定数量的比特,其中,所述第一预定数不同于所述第三预定数,所述第二预定数是 与第四预定数量不同。
    • 5. 发明申请
    • Low-profile air conditioning register
    • 低调的空调寄存器
    • US20080146139A1
    • 2008-06-19
    • US11987038
    • 2007-11-27
    • Nobuhiro TeraiMinoru ShibataTakahiko Sato
    • Nobuhiro TeraiMinoru ShibataTakahiko Sato
    • B60H1/34
    • B60H1/3421B60H2001/3471
    • A low-profile air conditioning register is provided with a retainer, a bezel and a plurality of downstream fins. The bezel is arranged in such a manner as to position a lower long side of an opening of a passage portion in a downstream than an upper long side. The angle formed between a flange portion and the ventilation direction of the retainer is equal to or more than 60°. Further, the length of a corresponding line to a short side of the opening in a surface which is orthogonal to the ventilation direction is equal to or less than 35 mm. Further a lower inner wall in the passage portion is inclined with respect to the ventilation direction in such a manner as to become lower toward a downstream side. The lower inner wall surface has a length equal to or less than 10 mm along a thickness direction of the flange portion.
    • 低调空调装置设置有保持器,挡板和多个下游翅片。 挡板布置成使得通道部分的开口的下长边位于比上长边的下游位置。 在凸缘部分和保持器的通气方向之间形成的角度等于或大于60°。 此外,与通气方向正交的表面中的开口的短边的对应线的长度等于或小于35mm。 此外,通道部分中的下部内壁相对于通气方向倾斜,朝向下游侧变低。 下部内壁面沿凸缘部的厚度方向的长度为10mm以下。
    • 7. 发明申请
    • Vehicular shock absorbing body
    • 车辆减震体
    • US20050116456A1
    • 2005-06-02
    • US10988841
    • 2004-11-16
    • Hiroyuki TajimaTakahiko SatoOsamu FukawataseTakeaki Kato
    • Hiroyuki TajimaTakahiko SatoOsamu FukawataseTakeaki Kato
    • B60R21/00B60R21/02B60R21/04B60R21/045
    • B60R21/045B60R2021/0051B60R2021/0414
    • The invention provides a vehicular shock absorbing body which absorbs a shock by a grid-like rib formed on a support plate portion and can inhibit a load point at an initial stage and a terminal stage, in a load-displacement (F-S) curve of the vehicular shock absorbing body. A shock absorbing body (40) used for absorbing a shock in a vehicle and made of a synthetic resin, is provided with a support plate portion (42), and a shock absorbing portion (45) formed in a grid shape on the support plate portion (42) by a plurality of thin ribs (44, 44), and plastically deforming at a time of applying a shock load so as to be absorbable a shock energy. A notch (a leading end side notch) 48 is formed between grid crossing points (46) in the thin rib (44) from a leading end side, and a notch (a root side notch) 50 is formed from a root side of the grid crossing points (46) so as to include the support plate portion (42), thereby inhibiting a load point from being generated at an initial stage and a terminal stage in the F-S curve.
    • 本发明提供了一种车辆冲击吸收体,其通过形成在支撑板部分上的格栅状肋吸收冲击,并且能够抑制在初始阶段和末端阶段的载荷位置(FS)曲线中的载荷点 车辆减震体。 用于吸收车辆中的冲击并由合成树脂制成的减震体(40)设置有支撑板部分(42)和在支撑板上形成为格子状的冲击吸收部分(45) 部分(42)由多个薄肋(44,44)构成,并且在施加冲击载荷时塑性变形以便可吸收冲击能。 从前端侧在薄肋(44)的格栅交叉点(46)之间形成有切口(前端侧切口)48,并且从切口(根侧切口)50的根侧形成有切口 栅格交叉点(46),以包括支撑板部分(42),从而阻止在FS曲线的初始阶段和终端阶段产生负载点。
    • 10. 发明授权
    • Memory device and memory control for controlling the same
    • 内存设备和内存控制控制相同
    • US08493400B2
    • 2013-07-23
    • US12981075
    • 2010-12-29
    • Takahiko Sato
    • Takahiko Sato
    • G06F12/06G06F12/02
    • G06F9/345G06T1/60G11C8/12H04N19/423H04N19/433
    • A memory device includes: a memory cell array which stores two-dimensionally arranged data in a plurality of memory unit regions selected by an address; an internal address control unit which generates an internal address which selects a memory unit region according to an external address; and a decoder which decodes the internal address and selects a memory unit region. The plurality of memory unit regions store data arranged in a first direction from among two-dimensionally arranged data according to a least-significant bit group of the internal address and store data arranged in a second direction from among the two-dimensionally arranged data according to a most-significant bit group of the address. The internal address control unit successively generates an internal address corresponding to the scan direction according to a scan direction control signal which controls a plurality of scan directions including at least an oblique direction of the two-dimensionally arranged data.
    • 一种存储器件包括:存储单元阵列,其存储由地址选择的多个存储器单元区域中的二维布置数据; 内部地址控制单元,其生成根据外部地址选择存储单元区域的内部地址; 以及解码器,其对内部地址进行解码并选择存储器单元区域。 多个存储单元区域根据内部地址的最低有效位组存储从二维排列的数据中排列在第一方向上的数据,并且根据第二方向从第二方向存储布置在二维布置数据中的数据 一个最重要的位组的地址。 内部地址控制单元根据扫描方向控制信号连续地产生与扫描方向相对应的内部地址,该扫描方向控制信号控制至少包括二维布置数据的倾斜方向的扫描方向。