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1. 发明授权

US06754126B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US06754126B2
公开(公告)日：2004-06-22
申请号：US10106597
申请日：2002-03-27
申请人： Shusaku Yamaguchi , Toshiya Uchida , Yoshimasa Yagishita , Yoshihide Bando , Masahiro Yada , Masaki Okuda , Hiroyuki Kobayashi , Kota Hara , Shinya Fujioka , Waichiro Fujieda
发明人： Shusaku Yamaguchi , Toshiya Uchida , Yoshimasa Yagishita , Yoshihide Bando , Masahiro Yada , Masaki Okuda , Hiroyuki Kobayashi , Kota Hara , Shinya Fujioka , Waichiro Fujieda
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C8/12 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4087 , G11C2211/4061 , G11C2211/4062
摘要： A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.
摘要翻译：形成多个第一存储块和用于再现第一存储块的数据的第二存储块。当读命令和刷新命令彼此冲突时，读控制电路根据刷新命令访问第一存储块，并通过使用第二存储块再现读数据。当写命令和刷新命令彼此冲突时，写控制电路根据命令接收的顺序操作存储块。因此，可以在不被用户识别的情况下进行刷新操作。即，可以提供用户友好的半导体存储器。

2. 发明申请

US20100146201A1 MEMORY DEVICE, MEMORY CONTROLLER AND MEMORY SYSTEM 有权
公开(公告)号：US20100146201A1
公开(公告)日：2010-06-10
申请号：US12612215
申请日：2009-11-04
申请人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G06F12/00
CPC分类号： G11C11/406 , G11C7/1027 , G11C8/12 , G11C11/40618 , G11C11/4087
摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

3. 发明授权

US07323789B2 Multiple chip package and IC chips 有权
标题翻译：多芯片封装和IC芯片
公开(公告)号：US07323789B2
公开(公告)日：2008-01-29
申请号：US11043993
申请日：2005-01-28
申请人： Fusao Seki , Tatsushi Otsuka , Masanori Kurita , Shinnosuke Kamata , Toshiya Uchida , Hiroyoshi Tomita , Hiroyuki Kobayashi
发明人： Fusao Seki , Tatsushi Otsuka , Masanori Kurita , Shinnosuke Kamata , Toshiya Uchida , Hiroyoshi Tomita , Hiroyuki Kobayashi
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C5/063 , H01L2224/49113 , H01L2924/3011 , H01L2924/00
摘要： A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a memory chip at portion near the side and the other side respectively. The clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad. A plurality of clock signals are supplied from the logic chip to the memory chip, and a plurality of return clock signals are returned from the memory chip to the logic chip.
摘要翻译：时钟输出板和返回时钟接收焊盘设置在集成电路芯片的靠近侧面的部分和与集成电路芯片的与侧面相反的另一侧的部分的逻辑芯片上。时钟接收垫分别在靠近侧面和另一侧的部分设置在存储器芯片上。时钟接收板电连接到时钟输出板和返回时钟接收板。多个时钟信号从逻辑芯片提供给存储器芯片，并且多个返回时钟信号从存储器芯片返回到逻辑芯片。

4. 发明授权

US06829195B2 Semiconductor memory device and information processing system 有权
标题翻译：半导体存储器件和信息处理系统
公开(公告)号：US06829195B2
公开(公告)日：2004-12-07
申请号：US10227430
申请日：2002-08-26
申请人： Toshiya Uchida , Hiroyuki Kobayashi
发明人： Toshiya Uchida , Hiroyuki Kobayashi
IPC分类号： G11C800
CPC分类号： G11C7/1036 , G11C7/1006
摘要： A semiconductor memory device capable of shortening the command supply interval during random access and thus improving the transfer rate of input/output data. In response to a write command, identical data is written into multiple memory banks having identical addresses assigned thereto. At this time, a bank selection circuit sequentially selects the memory banks to initiate write operations in a staggered manner. Since the write operation can be started before all memory banks become idle, the interval between the supply of read command and the supply of write command can be shortened. Consequently, the number of commands supplied per given time can be increased, and since data signal can be input/output more frequently than in conventional devices, the data transfer rate (data bus occupancy) improves. As a result, the performance of a system to which the semiconductor memory device is mounted can be enhanced.
摘要翻译：一种半导体存储器件，其能够缩短随机存取期间的指令供给间隔，从而提高输入/输出数据的传送速率。响应于写入命令，将相同的数据写入具有分配给其的相同地址的多个存储体。此时，存储体选择电路按顺序选择存储体以交错方式开始写入操作。由于可以在所有存储体空闲之前开始写入操作，所以可以缩短读取命令的供给与写入命令的供给之间的间隔。因此，可以增加每给定时间提供的命令数，并且由于数据信号可以比常规设备更频繁地输入/输出，所以数据传输速率（数据总线占用）提高。结果，可以提高安装半导体存储器件的系统的性能。

5. 发明授权

US06728157B2 Semiconductor memory 有权
公开(公告)号：US06728157B2
公开(公告)日：2004-04-27
申请号：US10335948
申请日：2003-01-03
申请人： Yoshimasa Yagishita , Toshiya Uchida , Yoshihide Bando , Hiroyuki Kobayashi , Shusaku Yamaguchi , Masaki Okuda
发明人： Yoshimasa Yagishita , Toshiya Uchida , Yoshihide Bando , Hiroyuki Kobayashi , Shusaku Yamaguchi , Masaki Okuda
IPC分类号： G11C700
CPC分类号： G11C11/4087 , G11C11/406
摘要： A plurality of memory blocks is allocated the same address spaces to write the same data therein, and is operable independently of one another. One of the memory blocks is selected as a refresh block that performs a refresh operation, in response to a refresh command, while another one of the memory blocks is selected as a read block that performs a read operation, in response to a read command. Then, the plurality of memory blocks performs read operations at different timings so that the read operations overlap one another. Therefore, the semiconductor memory can receive read commands at intervals each of which is shorter than the execution time of a single read operation. As a result, externally supplied read commands can be responded to at high speed, and the data transmission rate during read operation can be improved.

6. 发明授权

US08588006B2 Semiconductor memory including switching circuit for selecting data supply 有权
标题翻译：半导体存储器包括用于选择数据提供的切换电路
公开(公告)号：US08588006B2
公开(公告)日：2013-11-19
申请号：US13570158
申请日：2012-08-08
申请人： Hiroyuki Kobayashi , Toshiya Uchida
发明人： Hiroyuki Kobayashi , Toshiya Uchida
IPC分类号： G11C7/10
CPC分类号： G11C11/4096 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C11/4076 , G11C2207/105
摘要： A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal.
摘要翻译：提供半导体存储器，其包括：第一焊盘; 邻近所述第一焊盘设置的第二焊盘; 耦合到所述第一焊盘的第一输出缓冲器; 以及耦合到第二焊盘的第二输出缓冲器。第一垫通过金属耦合到第二垫。

7. 发明申请

US20060092752A1 Multiple chip package and IC chips 有权
标题翻译：多芯片封装和IC芯片
公开(公告)号：US20060092752A1
公开(公告)日：2006-05-04
申请号：US11043993
申请日：2005-01-28
申请人： Fusao Seki , Tatsushi Otsuka , Masanori Kurita , Shinnosuke Kamata , Toshiya Uchida , Hiroyoshi Tomita , Hiroyuki Kobayashi
发明人： Fusao Seki , Tatsushi Otsuka , Masanori Kurita , Shinnosuke Kamata , Toshiya Uchida , Hiroyoshi Tomita , Hiroyuki Kobayashi
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C5/063 , H01L2224/49113 , H01L2924/3011 , H01L2924/00
摘要： A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a memory chip at portion near the side and the other side respectively. The clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad. A plurality of clock signals are supplied from the logic chip to the memory chip, and a plurality of return clock signals are returned from the memory chip to the logic chip.
摘要翻译：时钟输出板和返回时钟接收焊盘设置在集成电路芯片的靠近侧面的部分和与集成电路芯片的与侧面相反的另一侧的部分的逻辑芯片上。时钟接收垫分别在靠近侧面和另一侧的部分设置在存储器芯片上。时钟接收板电连接到时钟输出板和返回时钟接收板。多个时钟信号从逻辑芯片提供给存储器芯片，并且多个返回时钟信号从存储器芯片返回到逻辑芯片。

8. 发明授权

US08264881B2 Semiconductor memory including pads coupled to each other 有权
标题翻译：半导体存储器包括彼此耦合的焊盘
公开(公告)号：US08264881B2
公开(公告)日：2012-09-11
申请号：US12624764
申请日：2009-11-24
申请人： Hiroyuki Kobayashi , Toshiya Uchida
发明人： Hiroyuki Kobayashi , Toshiya Uchida
IPC分类号： G11C7/00
CPC分类号： G11C11/4096 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C11/4076 , G11C2207/105
摘要： A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal.
摘要翻译：提供半导体存储器，其包括：第一焊盘; 邻近所述第一焊盘设置的第二焊盘; 耦合到所述第一焊盘的第一输出缓冲器; 以及耦合到第二焊盘的第二输出缓冲器。第一垫通过金属耦合到第二垫。

9. 发明授权

US08077537B2 Memory device, memory controller and memory system 有权
标题翻译：内存设备，内存控制器和内存系统
公开(公告)号：US08077537B2
公开(公告)日：2011-12-13
申请号：US12612215
申请日：2009-11-04
申请人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1027 , G11C8/12 , G11C11/40618 , G11C11/4087
摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.
摘要翻译：提供了一种存储装置，其中已经解决了由存储装置的刷新操作引起的有效带宽的减少，存储装置的存储器控制器及其存储器系统。响应于来自存储器控制器的命令操作的存储器件具有分别具有存储器核心的多个存储体，包括存储器单元阵列和解码器，并且由存储体地址选择; 以及控制电路，其响应于后台刷新命令使由所述存储器控制器设置的刷新对象组内的存储器核心依次执行对应于由所述存储器控制器设置的刷新突发长度的次数的刷新操作，并且响应于正常操作命令，在由存储器核心执行的刷新操作期间进一步使存储器内的存储器核心在刷新对象组之外并由存储体地址选择以执行与正常操作命令相对应的正常存储器操作在刷新目标银行。

10. 发明授权

US08004921B2 Memory device, memory controller and memory system 有权
公开(公告)号：US08004921B2
公开(公告)日：2011-08-23
申请号：US12612247
申请日：2009-11-04
申请人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1027 , G11C8/12 , G11C11/40618 , G11C11/4087
摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

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