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1. 发明授权

US06605536B2 Treatment of low-k dielectric films to enable patterning of deep submicron features 有权
公开(公告)号：US06605536B2
公开(公告)日：2003-08-12
申请号：US10143314
申请日：2002-05-10
申请人： Mona Eissa , Guoqiang Xing , Kenneth D. Brennan , Hyesook Hong
发明人： Mona Eissa , Guoqiang Xing , Kenneth D. Brennan , Hyesook Hong
IPC分类号： H01L2144
CPC分类号： H01L21/76826 , H01L21/31058 , H01L21/31116 , H01L21/31133 , H01L21/31138 , H01L21/76808 , H01L21/76835
摘要： Treating a low-k dielectric layer (104) using a highly oxidizing wet solution (e.g., H2SO4) to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130,132). The wet treatment is performed to either pre-treat a low-k dielectric (104) before forming the pattern (130,132) or during a rework of the pattern (130,132) to reduce resist poisoning.

2. 发明授权

US07129162B2 Dual cap layer in damascene interconnection processes 有权
标题翻译：大马士革互连工艺中的双盖层
公开(公告)号：US07129162B2
公开(公告)日：2006-10-31
申请号：US10429119
申请日：2003-05-02
申请人： Hyesook Hong , Guoqiang Xing , Ping Jiang
发明人： Hyesook Hong , Guoqiang Xing , Ping Jiang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76802 , H01L21/76808
摘要： Damascene methods for forming copper conductors (30, 130) are disclosed. According to the disclosed method, a dual cap layer (18, 20; 122, 124) is formed over an organosilicate glass insulating layer (16; 116, 120) prior to the etching of a via or trench toward an underlying conductor (12; 112). The dual cap layer includes a layer of silicon carbide (18; 124) and a layer of silicon nitride (20; 122). The silicon carbide layer (18; 124) and silicon nitride layer (20; 122) can be deposited in either order relative to one another. The silicon carbide layer (18; 124) maintains the critical dimension of the via or trench as it is etched through the insulating layer (16; 116, 120), while the silicon nitride layer (20; 122) inhibits the failure mechanism of resist poisoning. The method is applicable to single damascene processes, but may also be used in dual damascene copper processes.
摘要翻译：公开了用于形成铜导体（30,130）的镶嵌方法。根据所公开的方法，在将通孔或沟槽蚀刻到下面的导体（12;）之前，在有机硅酸盐玻璃绝缘层（16; 116,120）上形成双重覆盖层（18,20; 122,124）。 112）。双盖层包括碳化硅层（18; 124）和氮化硅层（20; 122）。碳化硅层（18; 124）和氮化硅层（20; 122）可以以相对于彼此的任何顺序沉积。碳化硅层（18; 124）在蚀刻通过绝缘层（16; 116,120）时保持通孔或沟槽的临界尺寸，而氮化硅层（20; 122）抑制抗蚀剂的失效机理中毒该方法适用于单镶嵌工艺，但也可用于双镶嵌铜工艺。

3. 发明授权

US06620560B2 Plasma treatment of low-k dielectric films to improve patterning 有权
公开(公告)号：US06620560B2
公开(公告)日：2003-09-16
申请号：US09975109
申请日：2001-10-11
申请人： Ping Jiang , Guoqiang Xing , Andrew J. McKerrow , Robert Kraft , Hyesook Hong
发明人： Ping Jiang , Guoqiang Xing , Andrew J. McKerrow , Robert Kraft , Hyesook Hong
IPC分类号： H01L21302
CPC分类号： H01L21/76835 , H01L21/31116 , H01L21/31138 , H01L21/76808 , H01L21/76826
摘要： Plasma treating a low-k dielectric layer (104) using an oxidation reaction (e.g., O2) to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130, 132). The plasma treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130, 132), during a rework of the pattern (130, 132), or between via and trench patterning to reduce resist poisoning.

4. 发明授权

US5880026A Method for air gap formation by plasma treatment of aluminum interconnects 失效
标题翻译：通过铝互连等离子体处理形成气隙的方法
公开(公告)号：US5880026A
公开(公告)日：1999-03-09
申请号：US991865
申请日：1997-12-16
申请人： Guoqiang Xing , Kenneth D. Brennan
发明人： Guoqiang Xing , Kenneth D. Brennan
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/50 , H01L23/522 , H01L23/48
CPC分类号： H01L21/7682 , H01L23/5222 , H01L2924/0002
摘要： An ultimate low k (k=1) gap structure for high speed logic devices in which the sidewalls fully or partially cover the gaps between the interconnects by dry etching the already formed aluminum interconnects after the photoresist has been stripped. This method is particularly useful for the subsequent deposition of silicon dioxide and for forming air gaps.
摘要翻译：用于高速逻辑器件的极限低k（k = 1）间隙结构，其中通过在光致抗蚀剂被剥离之后干燥蚀刻已经形成的铝互连，侧壁完全或部分地覆盖互连之间的间隙。该方法对于随后的二氧化硅沉积和用于形成气隙特别有用。

5. 发明授权

US06902939B2 Integrated circuit and method 有权
标题翻译：集成电路及方法
公开(公告)号：US06902939B2
公开(公告)日：2005-06-07
申请号：US10223643
申请日：2002-08-19
申请人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
发明人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
IPC分类号： H01L21/302 , H01L21/02 , H01L21/033 , H01L21/3065 , H01L21/311 , H01L21/8242 , H01L21/8246 , H01L27/115 , H01L21/00
CPC分类号： H01L27/11502 , H01L21/0332 , H01L21/31116 , H01L21/31144 , H01L27/10852 , H01L27/11507 , H01L28/55
摘要： A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
摘要翻译：在电极之间与电介质之间的电介质与绝缘扩散阻挡层之间的电介质接触电容器的通孔蚀刻包括基于F的电介质蚀刻和基于Cl和F的势垒蚀刻的两步蚀刻。

6. 发明授权

US06485988B2 Hydrogen-free contact etch for ferroelectric capacitor formation 有权
标题翻译：用于铁电电容器形成的无氢接触蚀刻
公开(公告)号：US06485988B2
公开(公告)日：2002-11-26
申请号：US09741650
申请日：2000-12-19
申请人： Shawming Ma , Guoqiang Xing , Rahim Kavari , Scott R. Summerfelt , Tomoyuki Sakoda
发明人： Shawming Ma , Guoqiang Xing , Rahim Kavari , Scott R. Summerfelt , Tomoyuki Sakoda
IPC分类号： H01L2100
CPC分类号： H01L21/31122 , H01L21/32136 , H01L21/76838 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/57 , H01L28/60
摘要： An embodiment of the instant invention is a method of forming a conductive contact to a top electrode (308 and 310 of FIG. 4d) of a ferroelectric capacitor comprised of a bottom electrode (304 of FIG. 4d) situated under the top electrode and a ferroelectric material (306 of FIG. 4d) situated between the top electrode and the bottom electrode, the method comprising the steps of: forming a layer (408 or 312 of FIG. 4) over the top electrode; forming an opening (414 of FIG. 4d) in the layer to expose a portion of the top electrode by etching the opening into the layer using a hydrogen-free etchant; and depositing conductive material (432 of FIG. 4d) in the opening to form an electrical connection with the top electrode.
摘要翻译：本发明的一个实施方案是一种形成导电接触的方法，该导电接触由位于顶部电极下方的底部电极（图4d的304）构成的铁电电容器的顶部电极（图4d的308和310）和铁电材料（图4d的306）位于顶部电极和底部电极之间，该方法包括以下步骤：在顶部电极上形成层（图4的408或312）; 在所述层中形成开口（图4d的414），以通过使用无氢蚀刻剂将所述开口蚀刻到所述层中来暴露所述顶部电极的一部分; 以及将导电材料（图4d的432）沉积在开口中以与顶部电极形成电连接。

7. 发明授权

US06410426B1 Damascene cap layer process for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的镶嵌帽层工艺
公开(公告)号：US06410426B1
公开(公告)日：2002-06-25
申请号：US09901392
申请日：2001-07-09
申请人： Guoqiang Xing , Ping Jiang
发明人： Guoqiang Xing , Ping Jiang
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/76802 , Y10S438/97
摘要： The invention describes a method for forming integrated circuit interconnects. A capping layer (50) is formed on a low k dielectric layer (40). The capping layer (50) and the low k dielectric layer (40) are etched to form a via and/or trench in the low k dielectric (4) which is filled with a conducting material (90) (95).
摘要翻译：本发明描述了一种用于形成集成电路互连的方法。在低k电介质层（40）上形成覆盖层（50）。蚀刻覆盖层（50）和低k电介质层（40）以在填充有导电材料（90）（95）的低k电介质（4）中形成通孔和/或沟槽。

8. 发明授权

US06576922B1 Ferroelectric capacitor plasma charging monitor 有权
标题翻译：铁电电容器等离子充电监视器
公开(公告)号：US06576922B1
公开(公告)日：2003-06-10
申请号：US10036799
申请日：2001-12-21
申请人： Shawming Ma , Guoqiang Xing , Stephen R. Gilbert
发明人： Shawming Ma , Guoqiang Xing , Stephen R. Gilbert
IPC分类号： H01L2358
CPC分类号： H01L22/34 , H01L28/55
摘要： Plasma charging devices and methods are disclosed for detecting plasma charging during semiconductor wafer processing. Charging monitors are disclosed having ferroelectric capacitance elements which can be preprogrammed prior to processing steps of interest, and then subsequently measured afterwards, in order to determine whether plasma related charging is a problem in the intervening processing steps.
摘要翻译：公开了用于在半导体晶片处理期间检测等离子体充电的等离子体充电装置和方法。公开了具有铁电电容元件的充电监视器，其可以在处理感兴趣的步骤之前被预编程，然后随后被测量，以便确定等离子体相关的充电是否是中间处理步骤中的问题。

9. 发明授权

US06492222B1 Method of dry etching PZT capacitor stack to form high-density ferroelectric memory devices 有权
公开(公告)号：US06492222B1
公开(公告)日：2002-12-10
申请号：US09739065
申请日：2000-12-18
申请人： Guoqiang Xing
发明人： Guoqiang Xing
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , G11C11/22 , H01L21/31122 , H01L27/11507 , H01L28/55
摘要： An embodiment of the instant invention is a method of fabricating a ferroelectric memory device (125 of FIG. 1) comprised of a top electrode (128 and 130 of FIG. 1) over a bottom electrode (124 of FIG. 1) with a ferroelectric material (126 of FIG. 1) located between the top electrode and the bottom electrode, the method comprising the steps of: providing a stack including: a layer of bottom electrode material, a layer of top electrode material, and a layer of ferroelectric material situated between the layer of bottom electrode material and the top electrode material; depositing a layer of hardmask material on the layer of top electrode material, the hardmask material being comprised of a refractory nitride; removing a portion of the layer of hardmask material thereby exposing a portion of the layer of top electrode material by subjecting the portion of the layer of hardmask material to a first gas comprised of a first chlorine-bearing species and argon; removing the exposed portion of the layer of top electrode material thereby exposing a portion of the layer of ferroelectric material by subjecting the exposed portion of the layer of top electrode material to a second gas comprised of nitrogen, a first oxygen-bearing species, argon, and a second chlorine-bearing species; removing the exposed portion of the layer of ferroelectric material thereby exposing a portion of the layer of bottom electrode material by subjecting the exposed portion of the ferroelectric material to a third gas comprised of a third chlorine-bearing species, a second oxygen-bearing species, and a first fluorine-bearing species; and removing the exposed portion of the layer of bottom electrode material by subjecting the exposed portion of the layer of bottom electrode material to a fourth gas comprised of nitrogen, argon, a fourth chlorine-bearing species, and a third oxygen-bearing species.

10. 发明授权

US06194313B1 Method for reducing recess for the formation of local interconnect and or plug trench fill for etchback process 失效
标题翻译：用于减少用于形成用于回蚀工艺的局部互连和/或插塞沟槽填充的凹部的方法
公开(公告)号：US06194313B1
公开(公告)日：2001-02-27
申请号：US09060971
申请日：1998-04-15
申请人： Abha R. Singh , Girish Anant Dixit , Wei-Yung Hsu , Guoqiang Xing
发明人： Abha R. Singh , Girish Anant Dixit , Wei-Yung Hsu , Guoqiang Xing
IPC分类号： H01L2144
CPC分类号： H01L21/76819 , H01L21/7684 , H01L21/76895
摘要： A method to reduce the effective recess in conductive plugs 220 by performing an oxide etch or oxide CMP, selective to the conductive material in question. This method can be used for any conductive plug 220 (e.g. aluminum, tungsten, copper, titanium nitride, etc.). In addition, this method is also applicable in contact, via, and trench (damascene) applications. Furthermore, this process can advantageously be used in logic, SRAM, and DRAM applications.
摘要翻译：通过对所讨论的导电材料进行选择性的氧化物蚀刻或氧化物CMP来减小导电插塞220中的有效凹部的方法。该方法可用于任何导电插头220（例如铝，钨，铜，氮化钛等）。此外，该方法也适用于接触，通孔和沟槽（镶嵌）应用。此外，该过程可以有利地用于逻辑，SRAM和DRAM应用中。

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